Microchip's CoreVectorBlox IP is a neural network accelerator designed for their PolarFire FPGAs, enabling power-efficient AI/ML inference at the edge. It allows software developers to implement trained neural networks (from frameworks like TensorFlow or ONNX). The CoreVectorBlox IP itself comprises a Matrix processor (MXP) for general neural network layers and an MXP CNN IP specifically for convolutional layers. This architecture allows it to be instantiated as either a single core accelerator or in multi-core configurations to distribute neural network workloads. This makes it ideal for applications requiring low power consumption and small form factors.
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Features and Benefits
- Multiple size configuration
- Overlay design that allows multiple networks to run on the same core and switch dynamically
- Configurable width (64b to 256b) AXI4 memory master for data access
- AXI4-Lite device for control and status
- Memory based with the ability to read inputs from memory-mapped master and write outputs
- Internal vector processor for general neural networks
- CNN accelerator for convolutional layers
- Multiple networks can be overlayed during the runtime and switched dynamically
- Possible to run simultaneous networks on a single CoreVectorBlox instantiation through time-slicing.
- The MXP CNN IP is responsible for executing the convolutional layers of CNNs.
Licensing Options
This IP core requires a free license to be requested and registered to use within Libero SoC Design Suite. A mymicrochip account will be required to complete this request, please login or create an account. Once logged in you can request, register, and install the CoreVectorBlox license.
Documentation
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| corevectorblox-2 | Link |