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CORERSDEC

CoreRSDEC is a register transfer level (RTL) generator that produces a Microsemi® fabricprogrammable gate array (FPGA)-optimized Reed-Solomon (RS) decoder core based on user-definedparameters.


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Features and Benefits

  • Parameterizable CoreRSDEC generator
  • Symbol widths from 3 to 8 bits
  • Supports shortened code in conventional mode decoding
  • Supports CCSDS-16 and CCSDS-8 decoding
  • CCSDS mode supports data decoding presented in dual basis

    • Licensing Options

    Available with Gold and Platinum licenses

    Documentation

    Title
    CoreRSDEC_HB.pdf Download