CoreFIFO is a fully configurable soft FIFO controller IP designed for Microchip FPGA families including PolarFire®, PolarFire SoC, RT PolarFire®, RT PolarFire SoC, RTG4™, SmartFusion®2, and IGLOO®2 devices. The IP provides flexible FIFO buffering functionality for managing data transfers between producer and consumer logic operating in either the same or independent clock domains. It supports both synchronous (single-clock) and asynchronous (dual-clock) FIFO architectures, making it well suited for clock domain crossing, data buffering, flow control, packet management, and high-throughput subsystem integration. CoreFIFO offers extensive configurability, including configurable data widths and depths, variable aspect ratios, internal or external memory support, dynamic threshold management, First-Word Fall-Through (FWFT), Prefetch operation, pipelined memory access, and ECC protection. The controller provides comprehensive status monitoring through FULL, EMPTY, Almost-FULL, Almost-EMPTY, write/read count, overflow, underflow, write acknowledge, and data valid indicators. Complete RTL source code and testbenches are included, enabling easy integration into FPGA and SoC designs while supporting high-performance and low-power implementation options.
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Features and Benefits
- Flexible FIFO Architecture
- Synchronous (single-clock) FIFO operation
- Asynchronous (dual-clock) FIFO operation
- Independent read and write clock domains
- Built-in clock domain crossing synchronization logic
- Advanced Data Buffering
- Configurable FIFO depth and width
- Configurable FIFO depth and width
- Read and write count monitoring
- Internal or external memory support
- Controller-only mode for custom memory implementations
- Status & Flow Control
- FULL and EMPTY flag generation
- Almost-FULL and Almost-EMPTY status flags
- Dynamic threshold configuration through input ports
- Overflow and underflow detection
- Write acknowledge (WACK)
- Data valid (DVLD) indication
- Performance Optimization
- First-Word Fall-Through (FWFT)
- Prefetch mode for reduced read latency
- Memory read data path pipelining
- High-speed and low-power optimization modes
- Support for large SRAM and micro SRAM implementations
Licensing Options
Free with any Libero License
Documentation
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| CoreFIFO_HB | Download |