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ZL30663

Status: In Production

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Device Overview

Summary

The ZL30663 offers three channels of Synchronous Ethernet (SyncE) packet clock synchronization. Using Microsemi’s miTimePLL timing technology, this device offers new and improved features for 5G transport and wireless infrastructure equipment.  Each device integrates all features required by line card PLL. High integration along with ultra-low jitter make these devices ideal for use in frequency translation from backplane clock to frequencies required by PHY devices, jitter filtering, and holdover in case both active and redundant timing cards fail.

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Under the same family, the ZL3069x offer one to three channels of Synchronous Ethernet (SyncE) packet clock synchronization for timing card interface. Also available is ZL3079x that support one to three independent timing channels of a combined hardware and software platform including IEEE 1588-2008 Precision Time Protocol Stack and Synchronization Algorithms.

Additional Features
  • Three independent DPLL channels
  • Precise phase/frequency measurement and tuning lower system latency to meet 4G LTE, 5G & Wireless Infrastructure
  • Precise chip-to-chip time interfaces use less backplane traces for 1PPS distribution for chassis systems
  • Split oscillator option lowers cost, lowers jitter, and provides redundancy
  • Excellent jitter performance of <300 fs RMS in the 12 kHz to 20 MHz band meets jitter requirements for 10G/40G and 100G PHYs
  • Two programmable ultra-low jitter synthesizers generate any frequency from 0.5 Hz to 1045 MHz
  • One programmable general purpose synthesizer generates any clock from 0.5 Hz to 180 MHz
  • 8 differential or 16 single ended ultra-low jitter outputs plus two general purpose CMOS outputs
  • Programmable output advancement/delay to accommodate trace delays or compensate for system routing paths
  • Up to three programmable digital PLLs/NCOs with loop bandwidth from 14 Hz to 470 Hz synchronize to any clock rate from 0.5 Hz to 900 MHz
  • Accepts up to 10 differential or 10 single ended input references
  • Full reference monitoring of electrical failures
  • Automatic hitless reference switching and digital holdover on reference fail with initial holdover accuracy better than 0.1 ppb
  • Any input reference can be fed with clock, sync (frame pulse), clock /sync pair or clock modulated with sync pulse (embedded PPS ePPS and embedded PP2S ePP2S)
  • Easy Configuration and dynamic programming via SPI/I2C interface
  • Factory programming available
  • Operates from a single crystal resonator or clock oscillator
  • Applications/Uses
    • Line card timing function for carrier network equipment compliant to ITU-T G.8262, G.8273.2, G.8273.4
    • Communications systems timed by any combination of Synchronous Ethernet, IEEE 1588 PTP, or GPS/GNSS
    • 5G wireless CU, DU, and RU systems
    • 5G systems with precise time requirements driven by advanced services such as carrier aggregation, coordinated multipoint, OTDOA location, etc.
    • Carrier routers, access aggregation, wireless backhaul,
    • SONET/SDH systems
Parametrics
Name
Value
Type
SyncE
DPLLs
3 or (3 NCO)
BW (Hz)
14-470
Inputs
10D/10SE
Input Frequency
0.5 Hz–900 MHz
Embedded PPS and EPP2S
Y
Diff. Outputs
8
CMOS Outputs
16 + 2
Output Frequency
0.5 Hz–1045 MHz
Low-Jitter APLLs
2
GP Clock Gen
1
Jitter (psRMS)
0.19

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RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
ZL30663LFG7
0.195600
1.613636
80
VFLGA
11x11x1mm
NiAu
e4
ZL30663
0.195600
1.613636
80
VFLGA
11x11x1mm
NiAu
e4
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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