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SY58051AU

Status: In Production

Features:

  • Three matched-delay input pair provide any logic function: AND, NAND, OR, NOR
  • DC to >10.7Gbps data rate throughput
  • DC to >8GHz clock fMAX
  • <160ps Any In-to-Out tpd
  • 20ps typical tr / tf
  • 0.2psRMS typical random jitter (data)
  • 2psPP typical deterministic jitter (data)
  • 5psPP typical total jitter (clock)
  • 46fsRMS typical additive phase jitter (clock)
  • Unique input termination and VT pin accepts AC- coupled and DC-coupled inputs (CML, PECL)
  • Internal 50Ω output source termination
  • Typical 400mV CML output swing (RL = 50Ω)
  • Internal 50Ω input termination
  • Power supply 2.5V ±5% or 3.3V ±10%
  • -40°C to +85°C industrial temperature range
  • Available in a 16-pin (3mm x 3mm) QFN package
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

The SY58051AU is an ultra-fast, low jitter universal logic gate with a guaranteed maximum data or clock throughput of 10.7Gbps or 8GHz, respectively. This AnyGate® differential logic device will produce many logic functions of two Boolean variables, such as AND, NAND, OR, NOR, DELAY, or NEGATION.The SY58051AU differential inputs include a unique internal termination design that allows access to the termination network throughout a VT pin. This feature allows the device to easily interface to different logic standards, both AC- and DC-coupled, without external resistor-bias and termination networks. The result is a clean, stub-free, low-jitter interface solution. The differential CML output is optimized for environments with internal 50Ω source termination and a 400mV output swing.The SY58051AU operates from a 2.5V or 3.3V supply and is guaranteed over the full industrial temperature range of –40°C to +85°C. The SY58051AU is part of Micrel’s Precision Edge® product family.

Additional Features
    • Three matched-delay input pair provide any logic function: AND, NAND, OR, NOR
    • Guaranteed AC performance over temperature and voltage:
      • DC to >10.7Gbps data rate throughput
      • DC to >8GHz clock fMAX
      • <160ps Any In-to-Out tpd
      • 20ps typical tr / tf
    • Ultra low-jitter design:
      • 0.2psRMS typical random jitter (data)
      • 2psPP typical deterministic jitter (data)
      • 5psPP typical total jitter (clock)
      • 46fsRMS typical additive phase jitter (clock)
    • Unique input termination and VT pin accepts AC- coupled and DC-coupled inputs (CML, PECL)
    • Internal 50Ω output source termination
    • Typical 400mV CML output swing (RL = 50Ω)
    • Internal 50Ω input termination
    • Power supply 2.5V ±5% or 3.3V ±10%
    • -40°C to +85°C industrial temperature range
    • Available in a 16-pin (3mm x 3mm) QFN package
Parametrics
Name
Value
Product Type
Universal Gate
Description
CML Universal Gate with Internal Input and Output Termination
Input
CML, PECL
Supply Voltage
2.5/3.3
Max Freq (GHz)
2
Max Prop Delay (ps)
160
Icc (mA)
250
Max Within Device Skew (ps)
25
OE
False
RPE
False
FSI
True
Input Mux
False
Input EQ
False
Output Type
CML
Output Voltage
2.5V

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RoHS Information

Part Number
Device Weight (g)
Shipping Weight (grams)
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
SY58051AUMG
0.021300
0.050000
16
VQFN
3x3x1.00mm
NiPdAu
e4
SY58051AUMG-TR
0.021300
0.801700
16
VQFN
3x3x1.00mm
NiPdAu
e4
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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