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TU0372

Download Application Note
Title
Title
Interfacing SmartFusion2 SoC FPGA with DDR3 Memory Through MDDR Controller System Builder Flow Tutorial
Name
Name
TU0372
Date
Date
05/09/2021
Description
Description
This tutorial describes how to create a hardware design using System Builder to access an external DDR3 memory through the built-in hard ASIC Microcontroller subsystem DDR (MDDR) in SmartFusion®2 SoC FPGAs. This tutorial also shows how to functionally verify the design using Bus Functional Model (BFM) simulation.

Files

Title Title Download Date Size
m2s_tu0372_df.zip 150.7 MB 11/19/2021 m2s_tu0372_df.zip Download 11/19/2021 150.7 MB