The DDR Read IP is a high-performance memory interface designed to retrieve continuous bursts of data from DDR memory, primarily for video processing applications. It reads stored video frames line-by-line and outputs data in real time for downstream processing or display pipelines. The IP operates in conjunction with a video arbiter, which converts read requests into AXI4 transactions. Internally, the design includes FIFO buffers for clock domain crossing, ensuring smooth data flow between the DDR interface and pixel clock domain. It supports configurable resolutions and data widths, allowing users to tailor the IP for various video formats. The read controller generates addresses based on frame start address and line offsets, enabling efficient sequential access to frame data.
Log in to myMicrochip to access tools and benefits. Sign up in just one minute.
Maximize Your Experience: Reap the Personalized Advantages by Completing Your Profile to Its Fullest. Update Here
Stay in the loop with the latest from Microchip. Update your profile while you are at it. Update Here
Complete your profile to access more resources. Update Here
true
Features and Benefits
- Video Frame Read Support
- Sequential frame line reading
- Frame-based address generation
- High-Speed Streaming
- Continuous burst read capability
- AXI4 Stream output
- Buffering Mechanism
- FIFO-based clock domain crossing
- Pixel clock domain support
- Flexible Configuration
- Supports multiple resolutions
- Adjustable pixel widths
- Efficient Addressing
- Automatic address increment
- Frame reset handling
Licensing Options
Free with any Libero license
Documentation
|
Title
|
||
|---|---|---|
| DDR Read IP User Guide | Download |