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CoreMemCtrl


The CoreMemCtrl is an advanced high-performance bus (AHBL) slave component that interfaces toexternal flash and SRAM memory devices. Both synchronous and asynchronous SRAM are supported.


Features and Benefits


  • Provides an AHB interface to external memory devices.
  • Configurable external memory interface, up to 4 chip select for synchronous/asynchronous SRAM.
  • Interfaces to external flash and either synchronous or asynchronous external SRAM.
  • Supports 32-bit word, 16-bit halfword, and 8-bit byte accesses to SRAM..
  • The locations of flash and SRAM in the address space can be swapped by asserting the REMAP
  • Licensing Options


    Free with any Libero License

    Documentation


    Title
    CoreMemCtrl_HB.pdf Download



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