The CNN Accelerator IP achieves accelerated CNN inference through single-clock-cycle parallel execution of digital signal processing (DSP) operations. A CNN consist of several types of layers connected in sequence like Convolution, Maxpool, ReLU, Fully connected layer, etc. The IP executes some of these layers sequentially and some of the layers simultaneously. The CNN accelerator IP interfaces to a DDR arbiter that enables multiple reads and writes.
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Features and Benefits
- Hardware Acceleration for CNN Inferencing :
- Performs multiple DSP operations in a single clock cycle for acceleration.
- Executes various CNN layers:
- Some layers are executed sequentially.
- Some layers are executed simultaneously.
- Layer and Data Management :
- Supports common CNN layers: Convolution, Maxpool, ReLU, Fully Connected layer, etc.
- Internal Architecture and Interfaces :
- Includes a Scheduler to manage sequencing from frame start to final output computation.
- Interfaces to a DDR arbiter for multiple reads and writes.
- DDR Channels :
- Two read channels
- One write channel
- Data Path and Processing Modules :
- Converts data from DDR interface clock to CNN system clock.
Licensing Options
Free with any Libero License
Documentation
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| Microsemi_UG0943_CNN_Accelerator_IP_User_Guide.pdf | Download |