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MIV_RV32IMA_L1_AHB

The MIV_RV32IMA_L1_AHB is a softcore processor designed to implement the RISC-V instruction set for use in Microchip FPGAs. The processor is based on Rocket-Chip, an open source high-performance single-issue, in-order execution pipeline 32-bit RISC-V core.


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Features and Benefits

  • Designed for FPGA soft-core implementation.
  • Integrated 8Kbytes instructions cache and 8Kbytes data cache.
  • A Platform-Level Interrupt Controller (PLIC) can support up to 31 programmable interrupts with a single priority level.
  • Supports the RISC-V standard RV32IMA ISA.
  • On-Chip debug unit with a JTAG interface.

    • Licensing Options

    Free with any Libero License

    Documentation

    Title
    MIV_RV32IMA_L1_AHB_HB.pdf Download