Clock to Data margin training of the IOD interface maximizes the valid window by continuously monitoring and controlling the delays using dynamic delay control signals. This operation is used to compensate for the PVT variations with high-speed source synchronous interfaces. This IP is recommended to be used for clock data training for MIPI interface.
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Features and Benefits
- Supports MIPI training through dynamic delay control signals of PF_IOD_GENERIC_RX component and LP signal
- Supports 256 tap delays for bit alignment
- Supports Manual Training and Auto Re-training modes
Licensing Options
Free with any Libero license
Documentation
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| MIPI Training Lite User Guide | Download |