We detect you are using an unsupported browser. For the best experience, please visit the site using Chrome, Firefox, Safari, or Edge. X
Maximize Your Experience: Reap the Personalized Advantages by Completing Your Profile to Its Fullest. Update Here
Stay in the loop with the latest from Microchip. Update your profile while you are at it. Update Here
Complete your profile to access more resources. Update Here
Cross-reference search
❮ ❯

COREAXITOAHBL

The CoreAXItoAHBL IP core is an Advanced eXtensible Interface (AXI) slave and an Advanced HighperformanceBus Lite (AHB-Lite) master. This provides an interface (bridge) between the AXI domainand AHB-Lite domain.


Buy Now

Features and Benefits

  • Provides an interface (bridge) between the Advanced eXtensible Interface (AXI) domain andAdvanced High-performance Bus Lite (AHB-Lite) domain
  • Supports both AXI3 and AXI4 protocol
  • Makes alternate AXI write and AXI read transactions possible
  • Supports AXI data bus width of 32-bits, with transfer size of 32/16/8 bit
  • Supports AXI data bus width of 64-bits, with transfer size of 64/32/16/8 bit
  • Maximum number of AXI beats or transfers of 256 when AXI4 interface is selected

    • Licensing Options

    Free with any Libero License

    Documentation

    Title
    CoreAXItoAHBL_HB.pdf Download



    Live Chat

    Need Help?

    Privacy Policy