CoreAXI4ProtoConv is designed for high throughput data transfer between the AXI4 Memory-Mapped and AXI4-Stream interfaces. The CoreAXI4ProtoConv supports the Memory Mapped to Stream (MM2S) and Stream to MemoryMapped (S2MM) conversion independently in a full duplex like method.
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Features and Benefits
- CoreAXI4ProtoConv core is fully compliant with the AXI4-Lite Interface, AXI4 Interface and AXI4-Stream Interface.
- Configurate AXI4 and AXI4 Stream Data Width : 32,64,128,256 and 512.
- Configurable Address Width.
- Supports configurable in-determinate AXI4-Stream transfers when S2MM (Stream to Memory Map) is enabled.
- Supports configurable little endian to big endian conversion.
- Supports configurable FIFO buffers and configurable packet-based FIFO (store and forward).
Licensing Options
Free with any Libero License
Documentation
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| CoreAXI4ProtoConv User Guide | Download |