Flexible USXGMII Integration for Modern Ethernet Systems
Our in-house CoreUSXGMII FPGA solution for PolarFire® and PolarFire SoC FPGAs implements the Universal Serial Media Independent Interface (USXGMII) to carry a single Ethernet port between the Media Access Control (MAC) and physical layer (PHY) transceiver over one Serializer/Deserializer (SerDes) link. It supports 1G, 2.5G, 5G and 10G data rates using a 64-bit XGMII interface on the MAC side and a 10.3125 Gbps serial link on the transceiver side. Designed for full-duplex operation, the IP enables efficient, high-speed MAC-to-PHY connectivity for compact Ethernet designs.
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Integrate IP and Connect MAC–PHY via SerDes
- Convey single-network ports over a USXGMII MAC-PHY interface (USXGMII-S only—USXGMII copper PHY: EDCS-1150953)
- Supports operating speed rates of 1G/2.5G/5G/10G
- MAC-side interface is 64-bit XGMII
- Operates system interface in full-duplex mode only
- Provides a 10.3125 Gbps serial link on the transceiver side
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