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Low Power FPGA and SoC Solutions Anti-Tamper Temperature Range Temperature Range Temperature Range Defense Packages

Building Defense Infrastructure With FPGAs

With demanding environments, thermal constraints and extreme security requirements, designing effective defense systems is a challenge. Choosing the right FPGA supplier is critical to your long-term mission success.

Security

Extensive anti-tamper capabilities that enable foreign military sales
Cryptographically assured supply chain
Side channel-resistant crypto co-processor
Dual Physically Unclonable Function (PUF)

Full Temperature Grade Offerings to Meet Defense Requirements

Lower power to meet rugged thermal environments
Industrial (−40°C to 100°C), automotive (−40°C to 125°C) and military (−55°C to 125°C) temperature ranges
Rugged military temperature packages

Unrivaled Power Efficiency for a Mid-Range FPGA

Compare the power efficiency between our PolarFire FPGA and a leading FPGA from one of our competitors.

Microchip PolarFire FPGA 3.5W, 59.8°C, 24.2 FIT, 28 nm

3.5W
59.8°C
24.2 FIT
28 nm

Competitor X FPGA 6.0W, 81.3°C, 96.3 FIT, 16nm

6.0W
81.3°C
96.3 FIT
16 nm

Explore Our FPGAs and SoCs To Build Your Defense Infrastructure

Anti-Tamper Features

The PolarFire family of products contains extensive anti-tamper features to customize your response to the threats your equipment may face:

Three analog windowed voltage detectors giving you high and low trip points for each critical supply (Vdd, Vdd18, Vdda25)
A digital windowed temperature sensor providing you a high and low die temperature.
Raw voltage and temperature values from the built-in sensors

Explore the Anti-Tamper Features of Our FPGAs

Flag Name	Description
MESH_ERROR	Active mesh tamper flag. This flag is asserted whenever the active security mesh observes a mismatch between the actual metal mesh output and the expected output. This allows protection against invasive attacks, such as cutting and probing of traces using Focused Ion Beam (FIB) technology with an active metal mesh on one of the higher metal layers.
CLOCK_MONITOR_GLITCH	Asserted whenever the clock glitch monitor detects a pulse width violation.
CLOCK_MONITOR_FREQUENCY	Asserted whenever the clock frequency monitor observes a frequency mismatch between the 160 MHz and 2 MHz RC oscillators.
SCB_BUS_ERROR	Asserted when an error has been detected on the system controller bus.
LOCK_ERROR	Asserted when a single- or double-bit error is detected in the continuously monitored security lock segments.
DIGEST	Asserted when a requested digest check fails.
INST_BUFFER_ACCESS	The flag is asserted when read/write access is performed to system controller’s shared buffer using JTAG/SPI interface.
INST_DEBUG	Asserted when debug instruction executed.
INST_CHECK_DIGESTS	Asserted when an external digest check has been requested.
INST_EC_SETUP	Asserted when elliptic curve slave instructions have been used.
INST_FACTORY_PRIVATE	Asserted when factory JTAG/SPI instruction is executed.
INST_KEY_VALIDATION	Asserted when key validation protocol is requested.
INST_MISC	Asserted when uncategorized SPI slave instruction executed.
INST_PASSCODE_MATCH	Asserted when an attempt has made to match a passcode.
INST_PASSCODE_SETUP	Asserted when the one-time passcode protocol is initiated.
INST_PROGRAMMING	Asserted when an external programming instruction has been used.
INST_PUBLIC_INFO	Asserted when a request for device public information is issued.
INST_PASSCODE_FAIL	Asserted when the passcode match fails.
INST_KEY_VALIDATION_FAIL	Asserted when the key validation fails.
INST_UNUSED	Asserted when the unused instruction opcode is executed.
BITSTREAM_AUTHENTICATION_FAIL	Asserted when the bitstream authentication fails.
IAP_AUTO_UPDATE	Asserted if an IAP update occurs (either by IAP system service or auto-update at device boot).
IAP_AUTO_RECOVERY	Asserted if the IAP recovery procedure occurs.

TeraFire EXP-F5200B

Our PolarFire FPGAs include the TeraFire EXP-F5200B cryptography microprocessor. With a comprehensive suite of cryptographic algorithms, strong DPA countermeasures, high performance and CAVP certifications, PolarFire FPGAs break new ground in bringing strong cryptography to the FPGA market.

TeraFire EXP-F5200B-Supported Protocols/Features

TRNG: SP800-90A CTR_DRBG-256; SP800-90B (draft) NRBG
AES-128/192/256 E/D (ECB, CBC, CTR, OFB, CFB, GCM, Key wrap)
SHA-1/224/256/384/512
HMAC-SHA-1/224/256/384/512; GMAC-AES; CMAC-AES
SHA-256 Key Tree
ECC: NIST P256/384/521 and Brainpool P256/384/512 curves

KeyGen, KAS - ECC CDH, ECDSA SigGen and SigVer, PKG, PKV
IFC: 1024/1536/2048/3072/4096
RSA E/D; SSA_PKCS1_V1_5 SigGen and SigVer; ANSI X9.31 SigGen and SigVer
FFC: 1024/1536/2048/3072/4096
KAS—DH, DSA SigGen and SigVer

TeraFire EXP-F5200B NIST CAVP Certifications Available

AES: 3950, 3951
DSA: 1077
RSA: 2018
ECDSA: 867, 868

SHS: 3258, 3259
DRBG: 1153, 1154
HMAC: 2573

PUFs

Two PUFs in one:

SRAM-PUF
Bus-keeper PUF

The entire PUF is power gated.