Digital Signal Controllers (DSCs)

For many motor control designs, we suggest the dsPIC33CK single-core family, such as dsPIC33CK256MC506, for cost-optimized Field-Oriented Control (FOC) and the dsPIC33A family, such as dsPIC33AK512MC510 or dsPIC33AK128MC106, when higher performance and precision are needed. These DSCs combine a DSP engine with high-resolution PWMs, high-speed ADCs and integrated op amps/comparators to run sensorless FOC on BLDC, PMSM, IPM, stepper and ACIM motors while leaving CPU bandwidth for functional-safety diagnostics. For space-constrained designs, integrated motor drivers such as the dsPIC33CDVL64MC106, with LIN, and dsPIC33CDVC256MP506, with CAN FD, combine the DSC, MOSFET gate driver and transceiver in one package.

For fast digital power control loops, the dsPIC33A family is a strong fit, with the dsPIC33AK-MPS DSCs designed for high-density DC-DC power, auxiliary rails and SiC/GaN-based converters. It provides a 200 MHz, 32-bit core with Double-Precision (DP-FPU); high-resolution PWMs; multiple, 40 Msps, 12-bit ADCs; high-speed comparators and DACs with slope compensation, which support the deterministic, low-latency control loops used at high switching frequencies. It also adds Post-Quantum Cryptography (PQC) support for secure power-supply designs. For cost-optimized power designs, the dsPIC33C family with 100 MHz, 250 ps PWM, 3.5 Msps ADC remains a strong fit.

For advanced sensing, the dsPIC33A family, , such as dsPIC33AK256MPS306, integrates a 200 MHz DSP core, 12-bit ADCs up to 40 Msps (with a 16-bit oversampling mode), integrated op amps, high-speed comparators, 12-bit DACs and an Integrated Touch Controller (ITC). This on-chip Analog Front-End (AFE) lets designers place high-speed acquisition close to the sensor; run real-time filtering; FFT and sensor-fusion algorithms; and reduce external op amps, PGAs and comparators to save BoM and board space. dsPIC33 DSCs are well-suited to current, position, pressure, flow, fluid-level, ultrasonic and ML-based sensing where high-speed analog, deterministic latency and DSP math matter.

Choose based on required control performance, analog capability, safety, security and cost:

• dsPIC33A: Higher performance—200 MHz, 32-bit CPU with DP-FPU; ADCs up to 40 Msps; 78 pS resolution PWMs; high-speed, 5 ns comparators; integrated security accelerators, including PQC on selected devices, and functional-safety support, such as ISO 26262 ASIL B or IEC 61508 SIL 2 and are suited for demanding motor control, high-frequency digital power and advanced sensing
• dsPIC33C: High-performance and cost-optimized—100 MHz, single-/dual-core, 3.5 Msps ADCs; 250 ps PWMs; and functional safety support with secure boot/update and are suited for mainstream FOC and power conversion

Both families scale from as little as 28 pins and 32 KB Flash, so you can move up in performance while preserving your dsPIC^® code and ecosystem.

dsPIC33 DSCs combine analog, DSP, real-time control, functional-safety and security features in a single device, which can benefit control-loop-critical designs. A DSP core with single-cycle multiply-accumulate executes FIR/IIR/FFT math with low latency; code runs from Flash with zero wait states for deterministic timing; and tightly coupled peripherals (high-speed ADC, high-resolution PWM, op amps, comparators, PTG) offload the CPU.