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dsPIC33FJ64MC506

Status: Not Recommended for new designs

Features:

  • Operating Range: • DC – 40 MIPS (40 MIPS @ 3.0-3.6V, -40°C to +85°C) • Industrial temperature range (-40°C to +85°C) High-Performance DSC CPU: • Modified Harvard architecture • C compiler optimized instruction set • 16-bit wide data path • 24-bit wide instructions • Linear program memory addressing up to 4M instruction words • Linear data memory addressing up to 64 Kbytes • 83 base instructions: mostly 1 word/1 cycle • Sixteen 16-bit General Purpose Registers • Two 40-bit accumulators: - With rounding and saturation options • Flexible and powerful addressing modes: - Indirect, Modulo and Bit-Reversed • Software stack • 16 x 16 fractional/integer multiply operations • 32/16 and 16/16 divide operations • Single-cycle multiply and accumulate: - Accumulator write back for DSP operations - Dual data fetch • Up to ±16-bit shifts for up to 40-bit data Direct Memory Access (DMA): • 8-channel hardware DMA: • 2 Kbytes dual ported DMA buffer area (DMA RAM) to store data transferred via DMA: - Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing) • Most peripherals support DMA Interrupt Controller: • 5-cycle latency • 118 interrupt vectors • Up to 67 available interrupt sources • Up to 5 external interrupts • 7 programmable priority levels • 5 processor exceptions Digital I/O: • Wake-up/Interrupt-on-Change on up to 24 pins • Output pins can drive from 3.0V to 3.6V • All digital input pins are 5V tolerant • 4 mA sink on all I/O pins System Management: • Flexible clock options: - External, crystal, resonator, internal RC - Fully integrated PLL - Extremely low jitter PLL • Power-up Timer • Oscillator Start-up Timer/Stabilizer • Watchdog Timer with its own RC oscillator • Fail-Safe Clock Monitor • Reset by multiple sources Power Management: • On-chip 2.5V voltage regulator • Switch between clock sources in real time • Idle, Sleep and Doze modes with fast wake-up Timers/Capture/Compare/PWM: • Timer/Counters, up to nine 16-bit timers: - Can pair up to make four 32-bit timers - 1 timer runs as Real-Time Clock with external 32.768 kHz oscillator - Programmable prescaler • Input Capture (up to 8 channels): - Capture on up, down or both edges - 16-bit capture input functions - 4-deep FIFO on each capture • Output Compare (up to 8 channels): - Single or Dual 16-Bit Compare mode - 16-bit Glitchless PWM mode Communication Modules: • 3-wire SPI (up to 2 modules): - Framing supports I/O interface to simple codecs - Supports 8-bit and 16-bit data - Supports all serial clock formats and sampling modes • I2C™ (up to 2 modules): - Full Multi-Master Slave mode support - 7-bit and 10-bit addressing - Bus collision detection and arbitration - Integrated signal conditioning - Slave address masking • UART (up to 2 modules): - Interrupt on address bit detect - Interrupt on UART error - Wake-up on Start bit from Sleep mode - 4-character TX and RX FIFO buffers - LIN bus support - IrDA® encoding and decoding in hardware - High-Speed Baud mode - Hardware Flow Control with CTS and RTS • Enhanced CAN (ECAN™ module) 2.0B active (up to 2 modules): - Up to 8 transmit and up to 32 receive buffers - 16 receive filters and 3 masks - Loopback, Listen Only and Listen All Messages modes for diagnostics and bus monitoring - Wake-up on CAN message - Automatic processing of Remote Transmission Requests - FIFO mode using DMA - DeviceNet™ addressing support Motor Control Peripherals: • Motor Control PWM (up to 8 channels): - 4 duty cycle generators - Independent or Complementary mode - Programmable dead time and output polarity - Edge or center-aligned - Manual output override control - Up to 2 Fault inputs - Trigger for ADC conversions - PWM frequency for 16-bit resolution (@ 40 MIPS) = 1220 Hz for Edge-Aligned mode, 610 Hz for Center-Aligned mode - PWM frequency for 11-bit resolution (@ 40 MIPS) = 39.1 kHz for Edge-Aligned mode, 19.55 kHz for Center-Aligned mode • Quadrature Encoder Interface module: - Phase A, Phase B and index pulse input - 16-bit up/down position counter - Count direction status - Position Measurement (x2 and x4) mode - Programmable digital noise filters on inputs - Alternate 16-bit Timer/Counter mode - Interrupt on position counter rollover/underflow Analog-to-Digital Converters (ADCs): • Up to two ADC modules in a device • 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion: - 2, 4 or 8 simultaneous samples - Up to 32 input channels with auto-scanning - Conversion start can be manual or synchronized with 1 of 4 trigger sources - Conversion possible in Sleep mode - ±2 LSb max integral nonlinearity - ±1 LSb max differential nonlinearity CMOS Flash Technology: • Low-power, high-speed Flash technology • Fully static design • 3.3V (±10%) operating voltage • Industrial temperature • Low-power consumption
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Overview
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Development Environment
Similar Devices
RoHS Information
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Device Overview

Summary

dsPIC33F Motor Control Digital Signal Controller (DSC) with seamless migration options to PIC24 MCUs and dsPIC30F DSCs in similar packages.

Please consider this device dsPIC33FJ64MC506A

Additional Features
    Operating Range:
  • DC – 40 MIPS (40 MIPS @ 3.0-3.6V, -40°C to +85°C)
  • Industrial temperature range (-40°C to +85°C)High-Performance DSC CPU:
  • Modified Harvard architecture
  • C compiler optimized instruction set
  • 16-bit wide data path
  • 24-bit wide instructions
  • Linear program memory addressing up to 4M instruction words
  • Linear data memory addressing up to 64 Kbytes
  • 83 base instructions: mostly 1 word/1 cycle
  • Sixteen 16-bit General Purpose Registers
  • Two 40-bit accumulators:- With rounding and saturation options
  • Flexible and powerful addressing modes:- Indirect, Modulo and Bit-Reversed
  • Software stack
  • 16 x 16 fractional/integer multiply operations
  • 32/16 and 16/16 divide operations
  • Single-cycle multiply and accumulate:- Accumulator write back for DSP operations- Dual data fetch
  • Up to ±16-bit shifts for up to 40-bit dataDirect Memory Access (DMA):
  • 8-channel hardware DMA:
  • 2 Kbytes dual ported DMA buffer area (DMA RAM) to store data transferred via DMA:- Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing)
  • Most peripherals support DMAInterrupt Controller:
  • 5-cycle latency
  • 118 interrupt vectors
  • Up to 67 available interrupt sources
  • Up to 5 external interrupts
  • 7 programmable priority levels
  • 5 processor exceptionsDigital I/O:
  • Wake-up/Interrupt-on-Change on up to 24 pins
  • Output pins can drive from 3.0V to 3.6V
  • All digital input pins are 5V tolerant
  • 4 mA sink on all I/O pinsSystem Management:
  • Flexible clock options:- External, crystal, resonator, internal RC- Fully integrated PLL- Extremely low jitter PLL
  • Power-up Timer
  • Oscillator Start-up Timer/Stabilizer
  • Watchdog Timer with its own RC oscillator
  • Fail-Safe Clock Monitor
  • Reset by multiple sourcesPower Management:
  • On-chip 2.5V voltage regulator
  • Switch between clock sources in real time
  • Idle, Sleep and Doze modes with fast wake-upTimers/Capture/Compare/PWM:
  • Timer/Counters, up to nine 16-bit timers:- Can pair up to make four 32-bit timers- 1 timer runs as Real-Time Clock with external 32.768 kHz oscillator- Programmable prescaler
  • Input Capture (up to 8 channels):- Capture on up, down or both edges- 16-bit capture input functions- 4-deep FIFO on each capture
  • Output Compare (up to 8 channels):- Single or Dual 16-Bit Compare mode- 16-bit Glitchless PWM modeCommunication Modules:
  • 3-wire SPI (up to 2 modules):- Framing supports I/O interface to simple codecs- Supports 8-bit and 16-bit data- Supports all serial clock formats and sampling modes
  • I2C™ (up to 2 modules):- Full Multi-Master Slave mode support- 7-bit and 10-bit addressing- Bus collision detection and arbitration- Integrated signal conditioning- Slave address masking
  • UART (up to 2 modules):- Interrupt on address bit detect- Interrupt on UART error- Wake-up on Start bit from Sleep mode- 4-character TX and RX FIFO buffers- LIN bus support- IrDA® encoding and decoding in hardware- High-Speed Baud mode- Hardware Flow Control with CTS and RTS
  • Enhanced CAN (ECAN™ module) 2.0B active (up to 2 modules):- Up to 8 transmit and up to 32 receive buffers- 16 receive filters and 3 masks- Loopback, Listen Only and Listen All Messages modes for diagnostics and bus monitoring- Wake-up on CAN message- Automatic processing of Remote Transmission Requests- FIFO mode using DMA- DeviceNet™ addressing supportMotor Control Peripherals:
  • Motor Control PWM (up to 8 channels):- 4 duty cycle generators- Independent or Complementary mode- Programmable dead time and output polarity- Edge or center-aligned- Manual output override control- Up to 2 Fault inputs- Trigger for ADC conversions- PWM frequency for 16-bit resolution (@ 40 MIPS) = 1220 Hz for Edge-Aligned mode, 610 Hz for Center-Aligned mode- PWM frequency for 11-bit resolution (@ 40 MIPS) = 39.1 kHz for Edge-Aligned mode, 19.55 kHz for Center-Aligned mode
  • Quadrature Encoder Interface module:- Phase A, Phase B and index pulse input- 16-bit up/down position counter- Count direction status- Position Measurement (x2 and x4) mode- Programmable digital noise filters on inputs- Alternate 16-bit Timer/Counter mode- Interrupt on position counter rollover/underflowAnalog-to-Digital Converters (ADCs):
  • Up to two ADC modules in a device
  • 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion:- 2, 4 or 8 simultaneous samples- Up to 32 input channels with auto-scanning- Conversion start can be manual or synchronized with 1 of 4 trigger sources- Conversion possible in Sleep mode- ±2 LSb max integral nonlinearity- ±1 LSb max differential nonlinearityCMOS Flash Technology:
  • Low-power, high-speed Flash technology
  • Fully static design
  • 3.3V (±10%) operating voltage
  • Industrial temperature
  • Low-power consumption
Parametrics
Name
Value
Architecture
16-bit
Max CPU Speed (MHz)
80
CPU Speed (MIPS/DMIPS)
40
Program Memory Size (KB)
64
SRAM (KB)
8
Direct Memory Access Channels
8
Temperature Range (C)
-40 to 85
Operating Voltage Range (V)
3 to 3.6
Pin Count
64
Analog Peripherals
1-A/D 16x12-bit @ 500(ksps)
UART
2
SPI
2
I2C
2
Timers
9 x 16-bit 4 x 32-bit
Motor Control PWM Outputs
8
Input Capture
8
Max PWM outputs (including complementary)
16
Number of PWM Time Bases
2
Output Compare Channels
8
Number of CAN Modules
1
Type of CAN Module
CAN
Class B Hardware
Yes
Quadrature Encoder Interface
1

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RoHS Information

Part Number
Device Weight (g)
Shipping Weight (grams)
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
DSPIC33FJ64MC506A-E/PT
0.286700
2.487500
64
TQFP
10x10x1mm
Matte Tin
e3
DSPIC33FJ64MC506A-H/PT
0.286700
2.487500
64
TQFP
10x10x1mm
Matte Tin
e3
DSPIC33FJ64MC506A-I/PT
0.286700
2.487500
64
TQFP
10x10x1mm
Matte Tin
e3
DSPIC33FJ64MC506AT-E/PT
0.286700
0.574667
64
TQFP
10x10x1mm
Matte Tin
e3
DSPIC33FJ64MC506AT-H/PT
0.286700
0.574667
64
TQFP
10x10x1mm
Matte Tin
e3
DSPIC33FJ64MC506AT-I/PT
0.286700
0.574667
64
TQFP
10x10x1mm
Matte Tin
e3
DSPIC33FJ64MC506AT-I/PTVAO
0.286700
0.574667
64
TQFP
10x10x1mm
Matte Tin
e3
DSPIC33FJ64MC506-I/PT
0.286700
2.487500
64
TQFP
10x10x1mm
Matte Tin
e3
DSPIC33FJ64MC506T-I/PT
0.286700
0.574667
64
TQFP
10x10x1mm
Matte Tin
e3
DSPIC33FJ64MC506A-I/PTVAO
0.286700
2.487500
64
TQFP
10x10x1mm
Matte Tin
e3
DSPIC33FJ64MC506A-E/MR
0.232400
0.350000
64
QFN
9x9x0.9mm
Matte Tin
e3
DSPIC33FJ64MC506A-H/MR
0.232400
0.350000
64
QFN
9x9x0.9mm
Matte Tin
e3
DSPIC33FJ64MC506A-I/MR
0.232400
0.350000
64
QFN
9x9x0.9mm
Matte Tin
e3
DSPIC33FJ64MC506AT-E/MR
0.232400
0.370303
64
QFN
9x9x0.9mm
Matte Tin
e3
DSPIC33FJ64MC506AT-H/MR
0.232400
0.370303
64
QFN
9x9x0.9mm
Matte Tin
e3
DSPIC33FJ64MC506AT-I/MR
0.232400
0.370303
64
QFN
9x9x0.9mm
Matte Tin
e3
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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