CoreSDR_AXI is intended to provide a 64-bit advanced microcontroller bus architecture (AMBA®) advanced extensible interface (AXI) to an external single data rate (SDR) synchronous dynamic random access memory (SDRAM).
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Features and Benefits
- High performance, SDR controller for standard SDRAM chips and dual in-line memory (DIMMs)
- Accesses the AXI slave interface through the SmartFusion®2 REVFIC64 fabric interface
- Supports 8,16, and 32-bit memory
- Supports up to 1,024 MB of memory
Licensing Options
Free with any Libero license
Documentation
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| CoreSDR_AXI_HB | Download |