CoreGbE_MR is a high-performance Ethernet MAC (Media Access Control) and PCS (Physical Coding Sublayer) IP core. It is compliant with the IEEE 802.3-2022 specification and supports both 1 Gbps (1000BASE-X) and 2.5 Gbps (2500BASE-X) data rates. The core facilitates high-speed data transfer by providing an industry-standard AXI4-Stream interface for transmit and receive data paths and an AXI4-Lite interface for register-based configuration and management. On the line side, it utilizes a 20-bit transceiver (XCVR) PMA interface. Key functional features include hardware-based framing, FCS (CRC-32) generation and verification, jumbo frame support (up to 9216 bytes), and integrated 8b/10b encoding/decoding with an elastic buffer for robust clock domain management.
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Features and Benefits
- Complaince:
- Designed to comply with the IEEE 802.3-2022 specification.
- Data Rates:
- Supports both 1 Gbps and 2.5 Gbps data rates.
- Supported Interfaces:
- User sides: AXI4-Stream interface for both transmit (TX) and receive (RX) data paths.
- Register access: AXI4-Lite target interface.
- Line side: 20-bit Transceiver (XCVR) PMA interface for 1000BASE-X and 2500BASE-X operation
- MAC Features:
- Transmit: Handles Ethernet framing (preamble/SFD), programmable IPG, automatic pad insertion for short frames, and FCS generation.
- Receive: Performs CRC-32 verification, destination address filtering (hash-based), and optional FCS/padding removal.
- Traffic Management: Supports Jumbo frames (up to 9216 bytes), VLAN tags, Flow Control (Pause frames), and Wake-on-LAN detection.
- PCS Features:
- Encoding: Implements 8b/10b (16b/20b) encoding and decoding logic.
- Synchronization: Uses a state machine and word aligner to detect comma characters for proper alignment.
- Buffering: Includes an elastic buffer to manage clock domain crossing via idle sequence manipulation.
Licensing Options
Encrypted RTL free with Libero license
Documentation
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| CoreGbE_MR User Guide | Download |