We detect you are using an unsupported browser. For the best experience, please visit the site using Chrome, Firefox, Safari, or Edge. X
Maximize Your Experience: Reap the Personalized Advantages by Completing Your Profile to Its Fullest. Update Here
Stay in the loop with the latest from Microchip. Update your profile while you are at it. Update Here
Complete your profile to access more resources. Update Here

Block Diagram


The PolarFire SoC FPGA family offers scalable, flexible solutions for power-efficient, real-time compute in a variety of applications. Devices span a range of logic densities and package options to support diverse system requirements. Our PolarFire Core SoC FPGAs are cost-optimized variants that do not include high-speed SerDes and PCIe® endpoint/root port capabilities.

 FeaturesPolarFire® SoC FPGA
  MPFS025TMPFS095TMPFS160TMPFS250TMPFS460T
FPGA FabricK Logic Elements (4LUT + DFF)2393161254461
Math Blocks (18 × 18 MACC)682924987841420
LSRAM Blocks (20 kbits)843085208121460
uSRAM Blocks (64 × 12)204876149423524260
Total RAM Mbits1.86.711.317.631.6
uPROM Kbits194387415470553
User DLLs/PLLs8 each8 each8 each8 each8 each
Microprocessor Subsystem (MSS)Boot/monitor core1 × E51 core: RISC-V RV64IMAC, 625 MHz
Application cores4 × U54 cores; RISC-V RV64GC, 625 MHz
L2 Cache12 MB; configurable as Cache, Loosely Integrated Memory (LIM) or Scratchpad
Data securityDPA-resistant Athena Terafire® crypto coprocessor available in devices with the suffix "S"
Peripherals2 × Gigabit Ethernet MAC; MMC 5.1; 2 × CAN; 1 × QSPI; 2 × SPI 2 × I2C; 5 x UART; 1 x USB 2.0 OTG
 Note: PolarFire Core SoC FPGAs do not have high-speed SerDes lanes or PCI Express® Gen 2 endpoints/root ports.
High-Speed I/O250 Mbps to 12.5 Gbps SerDes Lanes44481620
PCIe® Gen 2 End Points/Root Ports422222
Total FPGA I/OHSIO + GPIO108276312372468
Total MSS I/OMSS I/O136136136136136

MSS DDR DB

MSS DDR Data Bus16/32216/322323232
  MPFS025TMPFS095TMPFS160TMPFS250TMPFS460T
Packaging
Commercial and Industrial
RoHS
Type/Size/PitchTotal User I/O: MSS-IO/HSIO/GPIO/XCVRs
Note: PolarFire Core SoC FPGAs do not have transceivers.
FCSG3253 (11 × 11, 11 × 14.5, 0.5 mm)102, 32, 48, 2102, 32, 48, 2   
FCSG536 (16 × 16, 0.5 mm) 136, 60, 84, 4136, 60, 108, 4136, 60, 108, 4 
FCVG484 (19 × 19, 0.8 mm)136, 60, 48, 4136, 60, 84, 4136, 60, 84, 4136, 60, 84, 4 
FCVG784 (23 × 23, 0.8 mm) 136, 144, 132, 4136, 144, 168, 8136, 144, 180, 8 
FCG1152 (35 × 35, 1.0 mm)   136, 144, 228, 16136, 180, 288, 20

Notes:

  1. L2 can be configured as cache or RAM. The minimum cache size is 128KB and max RAM size is 1920KB. This can be allocated in blocks of 128KB.
  2. 16-bit DDR data bus width for the FCSG325 package
  3. FCSG325 package dimensions for MPFS095T - 11 x 14.5, 0.5 mm
  4. These features are not available on the PolarFire Core SoC FPGA devices

PolarFire SoCs are offered with multiple speed grades, temperatures, and package combinations. All temperatures are specified as junction temperatures. The following illustration shows the ordering information.

Mi-V RISC-V Ecosystem


The Mi-V RISC-V Ecosystem is a comprehensive suite of tools and solutions co-developed by Microchip and industry partners to accelerate RISC-V adoption on PolarFire SoC FPGAs.

 PolarFire SoC Solutions


GitHub Resources


Whether you're developing cutting-edge embedded systems, exploring RISC-V®-based architecture or building AI/ML applications, you can refer to this page for resources such tools, software frameworks, design examples and documentation that are available to you on GitHub

Tools and Software Frameworks on GitHub


Getting Started with PolarFire SoCs


Kits and Programming Hardware


PolarFire® SoC Icicle Kit

General Purpose, Linux® Ready, PCIe®

  • General-purpose PolarFire SoC platform for Linux and MPU + FPGA evaluation
  • Full I/O and expansion, including PCIe Gen 2 x4 and rich peripheral set
  • Starter kit suitable for serious development, reference designs and system initial setup

PolarFire SoC Video Kit

Vision and Video,AI/ML, Cameras, HDMI®

  • Purpose-built for vision and video workloads
  • Native video interfaces: dual MIPI CSI-2® cameras and HDMI 2.0 in/out
  • Well suited for edge AI, imaging and video pipelines using PolarFire SoC fabric acceleration

PolarFire® SoC Discovery Kit

Low Cost, Compact, Learning and Prototyping

  • Lowest-cost entry point into PolarFire SoC and RISC‑V® development
  • Smaller FPGA and no PCIe, optimized for affordability and size
  • Great for learning, software initial setup and quick prototypes
Part Number: Quantity: Price per Unit (in USD): Total Amt:
FLASHPRO6

FlashPro6 offers exceptionally high performance through USB 3.0 that supports Serial Peripheral Interconnect (SPI) client and JTAG interfaces.

FLASHPRO5

FlashPro5 offers high performance through USB 2.0 that supports Serial Peripheral Interconnect (SPI) and JTAG interfaces.

FLASHPRO4

FlashPro4 is designed for JTAG programming of older Microchip FPGA families, including IGLOO, ProASIC3, SmartFusion, and Fusion. It is suitable for existing designs that do not require SPI Slave programming, advanced debugging, or high-speed programming

PolarFire SoC FPGA Videos


PolarFire SoC GitHub Introduction

This video provides an overview of key repositories, tools and documentation in GitHub to help you get started.

Debugging a Bare Metal Application

Learn to run and debug a bare metal app on the Icicle Kit using MMUART ports.

Creating a Bare Metal App for LIM

Configure the core, adjust memory and integrate with HSS for smooth operation.

Running Bare Metal Apps From DDR

Build HSS, program eMMC and boot a bare metal app from DDR memory.

Support


Live Chat

Need Help?

Privacy Policy