The PolarFire® SoC family delivers industry-leading power efficiency, excellent thermal performance and defense-grade security for intelligent, connected systems. Built around a deterministic, coherent RISC-V CPU cluster with deterministic L2 memory subsystem, this family of devices enables seamless development of Linux® and real-time applications.
The PolarFire SoC family now includes cost-optimized PolarFire Core SoC FPGAs devices for applications that don’t require high-speed serial transceivers. These new SoC FPGAs offer up to 460K logic elements and combine embedded RISC-V processing with a wide range of logic densities, packaging options, fast I/O and configuration flexibility to meet diverse performance, power and cost requirements.
The PolarFire SoC family now includes cost-optimized PolarFire Core SoC FPGAs devices for applications that don’t require high-speed serial transceivers. These new SoC FPGAs offer up to 460K logic elements and combine embedded RISC-V processing with a wide range of logic densities, packaging options, fast I/O and configuration flexibility to meet diverse performance, power and cost requirements.
The PolarFire SoC FPGA family offers scalable, flexible solutions for power-efficient, real-time compute in a variety of applications. Devices span a range of logic densities and package options to support diverse system requirements. Our PolarFire Core SoC FPGAs are cost-optimized variants that do not include high-speed SerDes and PCIe® endpoint/root port capabilities.
Notes:
PolarFire SoCs are offered with multiple speed grades, temperatures, and package combinations. All temperatures are specified as junction temperatures. The following illustration shows the ordering information.
Whether you're developing cutting-edge embedded systems, exploring RISC-V®-based architecture or building AI/ML applications, you can refer to this page for resources such tools, software frameworks, design examples and documentation that are available to you on GitHub
PolarFire SoCs combine a deterministic, coherent RISC-V CPU cluster with an L2 memory subsystem for real-time and Linux® applications. Explore comprehensive documentation, reference designs and development tools on GitHub to kick-start your development journey.
Browse tools and IP cores for RISC-V soft CPUs on our FPGAs with support for Libero® SoC Design Suite and SoftConsole.
VectorBlox SDK empowers AI/ML developers with tools for efficient Convolutional Neural Network (CNN) inference on PolarFire FPGAs and PolarFire SoC FPGAs. Access development tools, detailed documentation and practical examples on GitHub for your vision projects.
SmartHLS compiler enables high-level synthesis for PolarFire FPGA and PolarFire SoC FPGA designs, allowing you to write in C++ and convert C++ code into optimized RTL. Get started with tools, examples and guides on GitHub.
FlashPro6 offers exceptionally high performance through USB 3.0 that supports Serial Peripheral Interconnect (SPI) client and JTAG interfaces.
FlashPro5 offers high performance through USB 2.0 that supports Serial Peripheral Interconnect (SPI) and JTAG interfaces.
FlashPro4 is designed for JTAG programming of older Microchip FPGA families, including IGLOO, ProASIC3, SmartFusion, and Fusion. It is suitable for existing designs that do not require SPI Slave programming, advanced debugging, or high-speed programming
The PolarFire SoC Microprocessor Subsystem (MSS) configurator is a software tool to configure the PolarFire SoC microprocessor subsystem.
Libero SoC Design Suite offers high productivity with its comprehensive, easy-to-learn, easy-to-adopt development tools for designing with our FPGA device families.
SoftConsole is a software development environment for the rapid development of bare metal- and RTOS-based C/C++ software.
This video provides an overview of key repositories, tools and documentation in GitHub to help you get started.
Learn to run and debug a bare metal app on the Icicle Kit using MMUART ports.
Configure the core, adjust memory and integrate with HSS for smooth operation.
Build HSS, program eMMC and boot a bare metal app from DDR memory.
Create a custom Linux image, control GPIOs and interact with LEDs.
Build, debug and program a bare metal app for FPGA fabric using key tools.
Use drivers to build custom Linux® distributions and control MSS GPIOs and fabric LSRAM.
Learn how to create a design in Libero® SoC Design Suite, integrate APB interface-based IP and use SDIO registers.
Set up and access a PCIe NVMe™ drive from Linux® on the Icicle Kit.
Use MPFS GPIO and UART examples to handle interrupts in a bare metal application.
Learn Smart Debug features for FPGA and SoC debugging, including live probes and memory views.
Add and program custom packages to a Yocto image for testing on the Icicle Kit.
Visit our technical support portal If you need assistance with your PolarFire SoC FPGA-based design.
Try our discussions forum on our GitHub page. Browse the available database of questions and answers, post your questions and support others in the discussions.
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