The VSC8115 functions as a Clock and Data Recovery (CDR) unit for SONET/SDH-based equipment to derive highspeed timing signals. The VSC8115 recovers the clock from the scrambled NRZ data operating at 622.08Mb/s (STS-12/OC- 12/STM-4) or 155.52Mb/s (STS-3/OC-3/STM-1). After the clock is recovered, the data is retimed using an output flipflop. In the absence of a invalid signal, the PLL will lock to the reference clock, providing the downstream device a constant clock signal, and reducing the relocking time.
Performs clock and data recovery for OC-12 (STM-4) and OC-3 (STM-1) NRZ data
Low power: 188 mW typical power dissipation
High-speed outputs can be configured for LVPECL or LVDS levels
Signal and lock detect status outputs
PLL-bypass operation facilitates board debug process
Automatic lock to reference
Clock and Data Recovery
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