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SY89537L

Status: In Production

Features:

  • Integrated programmable synthesizer with multiple output dividers, fanout buffers, and clock drivers
  • Ideal for reference backup clock source or system test frequency source
  • Patent-pending unique input MUX isolates XTAL and reference inputs minimizes crosstalk
  • 87.15MHz to 700MHz output frequency range (with RFCK at 16.6MHz )
  • <100psPP total jitter
  • <7psRMS cycle-to-cycle jitter
  • <8psPP deterministic jitter
  • <0.7psRMS crosstalk induced jitter
  • <50ps bank-to-bank skew
  • Output bank synchronization control pin
  • LVPECL and LVDS outputs
  • TTL/CMOS compatible control logic
  • Four differential LVPECL output banks
  • One differential LVDS output bank with 3 output pairs
  • Separate output enable for each bank
  • 3.3V ±10% power supply (2.5V output capable)
  • Guaranteed over the industrial temperature range (-40°C to +85°C)
  • Available in 44-pin (7mm x 7mm) MLF® package
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

The SY89537L integrated programmable clock synthesizer and fanout is part of a precision PLL-based clock generation family optimized for enterprise switch, router, and multiprocessor server applications. This family is ideal for generating internal system timing requirements up to 700MHz for multiple ASICs, FPGAs, and NPUs. These devices integrate the following blocks into a single monolithic IC:
PLL (Phase-Lock-Loop) based synthesizer
Fanout buffers
Clock generator (dividers)
Logic translation (LVPECL, LVDS)

Five independently programmable output banksThis level of integration minimizes additive jitter and part-to-part skew associated with discrete alternatives, resulting in superior system-level timing with reduced board space and power. For applications that require a zero-delay function, see the SY89538L.

Additional Features
    • Integrated programmable synthesizer with multiple output dividers, fanout buffers, and clock drivers
    • Direct interface to crystal: 14MHz to 18MHz Input MUX accepts a reference and a crystal (XTAL) source
      • Ideal for reference backup clock source or system test frequency source
      • Patent-pending unique input MUX isolates XTAL and reference inputs minimizes crosstalk
    • Guaranteed AC performance:
      • 87.15MHz to 700MHz output frequency range (with RFCK at 16.6MHz )
      • <100psPP total jitter
      • <7psRMS cycle-to-cycle jitter
      • <8psPP deterministic jitter
      • <0.7psRMS crosstalk induced jitter
      • <50ps bank-to-bank skew
    • Output bank synchronization control pin
    • LVPECL and LVDS outputs
    • TTL/CMOS compatible control logic
    • Five independently programmable output frequency banks:
      • Four differential LVPECL output banks
      • One differential LVDS output bank with 3 output pairs
    • Separate output enable for each bank
    • 3.3V ±10% power supply (2.5V output capable)
    • Guaranteed over the industrial temperature range (-40°C to +85°C)
    • Available in 44-pin (7mm x 7mm) MLF® package
Parametrics
Name
Value
Product Type
Clock Synthesizers
Input Frequency (MHz) Crystal
25
PDB
False
OE
True
FSEL
True
CSEL
False
CLK
False
Ultra Low Power
False
Output Frequency Min. (MHz)
125

Documents

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Data Sheets

11/11/2015
743KB

User Guides

11/11/2015
342KB

Development tools data is currently unavailable.

RoHS Information

Part Number
Device Weight (g)
Shipping Weight (grams)
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
SY89537LMY
0.127600
0.722685
44
VQFN
7x7x0.9mm
Matte Tin
e3
SY89537LMY-TR
0.127600
0.620478
44
VQFN
7x7x0.9mm
Matte Tin
e3
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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