Status: In Production
The SY89250V is a differential PECL/ECL receiver/buffer in a space saving (2mm x 2mm) MLF® package. The device is functionally equivalent to the SY100EL16VC, but features a 70% smaller footprint. It provides a VBB output for either single-ended application or as a DC bias for AC-coupling to the device.The SY89250V provides an /EN input which is synchronized with the data input (D) signal in a way that provides glitchless gating of the QHG and /QHG outputs. When the /EN signal is LOW, the input is passed to the outputs and the data output equals the data input.
When the data input is HIGH and the /EN goes HIGH, it will force the QHG LOW and the /QHG HIGH on the next negative transition of the data input. If the data input is LOW when the /EN goes HIGH, the next data transition to a HIGH is ignored and QHG remains LOW and /QHG remains HIGH. The next positive transition of the data input is not passed on to the data outputs under these conditions. The QHG and /QHG outputs remain in their disabled state as long as the /EN input is held HIGH. The /EN input has no influence on the /Q output and the data input is passed on (inverted) to this output whether /EN is HIGH or LOW. This configuration is ideal for crystal oscillator applications, where the oscillator can be free running and gated on and off synchronously without adding extra counts to the output.
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