The MIV_RV32 is a processor core designed to implement the RISC-V instruction set for use in Microchip FPGAs.The core includes the industry standard JTAG interface to facilitate debug access. Three optional bus interfaces areavailable for peripheral and memory accesses: AHB, APB3, and AXI, which can be configured as AXI3 or AXI4.
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Features and Benefits
Designed for low power FPGA soft-core implementations
- Supports the RISC-V standard RV32I ISA with optional Multiply and Divide (M) and Compressed (C) extensions
- Tightly-Coupled Memory (TCM) is available and the size, up to 256 Kbytes, is defined by address range
- TCM APB Slave (TAS) to TCM
- Boot ROM feature to load an image and run from memory
Licensing Options
Free with any Libero License
Documentation
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| MIV_RV32 v3.1 User Guide | Download | |
| MIV_RV32 v3.1 Migration Guide | Download | |
| MIV_RV32 v3.1.2 Release Notes | Download | |
| PolarFire_MIV_RV32IMC_v21 | Download | |
| RISC-V External Debug Support | Download | |
| Supplementary RUP Information for MIV_RV32 v3.0 | Download | |
| The RISC-V Instruction Set Manual | Download | |
| The RISC-V Instruction Set Manual | Download | |
| MIV_RV32 v3.0 Handbook | Download | |
| MI-V RV32 Migration Guide | Download | |
| RN0236 Release Notes MIV_RV32 v3.0 | Download |