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SY89809L

500MHz 1:9 Diff. HSTL Fanout Buffer

Status: End of Life

Features:

  • 3.3V core supply, 1.8V output supply for reduced power
  • LVPECL and HSTL inputs
  • 9 differential HSTL (low-voltage swing) output pairs
  • HSTL outputs drive 50Ω-to-ground with no offset voltage
  • 500MHz maximum clock frequency
  • Low part-to-part skew (200ps max.)
  • Low pin-to-pin skew (50ps max.)
  • Available in 32-pin TQFP
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Device Overview

Summary

The SY89809L is a High-Performance Bus Clock Driver with 9 differential HSTL (High-Speed Transceiver Logic) output pairs. The part is designed for use in low-voltage (3.3V/1.8V) applications, which require a large number of outputs to drive precisely aligned, ultra-low skew signals to their destination. The input is multiplexed from either HSTL or LVPECL (Low-Voltage Positive-Emitter-Coupled Logic) by the CLK_SEL pin. The Output Enable (OE) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control.The SY89809L features low pin-to-pin skew (50ps max.) and low part-to-part skew (200ps max.)--performance previously unachievable in a standard product having such a high number of outputs. The SY89809L is available in a single space saving package, enabling a lower overall cost solution.

Additional Features
    • 3.3V core supply, 1.8V output supply for reduced power
    • LVPECL and HSTL inputs
    • 9 differential HSTL (low-voltage swing) output pairs
    • HSTL outputs drive 50Ω-to-ground with no offset voltage
    • 500MHz maximum clock frequency
    • Low part-to-part skew (200ps max.)
    • Low pin-to-pin skew (50ps max.)
    • Available in 32-pin TQFP
Parametrics
Name
Value
Description
2:9
Input
LVPECL/HSTL
Output
HSTL
Supply Voltage
3.3V
Max Freq (GHz)
0.5
Max Prop Delay (ps)
<1275
Icc (mA)
115
Max Within Device Skew (ps)
<200
OE
True
RPE
False
FSI
False
Input Mux
True
Input EQ
False

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