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SY100ELT23

Status: In Production

Features:

  • 3.0 ns typical propagation delay
  • <500ps output-to-output skew
  • Differential PECL inputs
  • 24mA TTL outputs
  • Flow-through pinouts
  • Internal 50kOhm pulldown resistors
  • Available in 8-pin SOIC package
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

The SY100ELT23 are dual differential PECL-to-TTL translators. Because PECL (Positive ECL) levels are used, only +5V and ground are required. The small outline 8-lead SOIC package and the low skew, dual gate design of the ELT23 makes it ideal for applications which require the tranlation of a clock and a data signal.The ELT23 is compatible with positive ECL 100K logic levels.

Additional Features
    • 3.0 ns typical propagation delay
    • <500ps output-to-output skew
    • Differential PECL inputs
    • 24mA TTL outputs
    • Flow-through pinouts
    • Internal 50kOhm pulldown resistors
    • Available in 8-pin SOIC package
Parametrics
Name
Value
Product Type
Logic Translators
Input
PECL
Output
TTL
Supply Voltage
5
Max Freq (GHz)
0.16
Max Prop Delay (ps)
3500
Icc (mA)
30
Max Within Device Skew (ps)
300
OE
True
RPE
False
FSI
False
Input Mux
False
Input EQ
False
Channels
Dual
Output Type
TTL
Output Voltage
2.5

Documents

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RoHS Information

Part Number
Device Weight (g)
Shipping Weight (grams)
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
SY100ELT23LZG
0.075000
0.163265
8
SOIC
3.90mm(.150in)
NiPdAu
e4
SY100ELT23ZG-TR
0.075000
0.250000
8
SOIC
3.90mm(.150in)
NiPdAu
e4
SY100ELT23LZG-TR
0.075000
0.250000
8
SOIC
3.90mm(.150in)
NiPdAu
e4
SY100ELT23ZG
0.075000
0.163265
8
SOIC
3.90mm(.150in)
NiPdAu
e4
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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