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SST25VF064C

Status: End of Life

Features:

  • Serial Interface Architecture – SPI Compatible: Mode 0 and Mode 3
  • Dual Input/Output Support
  • Flexible Erase Capability: Uniform 4 KByte sectors, Uniform 32 KByte overlay blocks, Uniform 64 KByte overlay blocks
  • Low Power Consumption: Active Read Current: 12 mA (typical @ 80 MHz, Standby Current: 5 µA (typical)
  • Fast Erase and Page-Program: Chip-Erase Time: 35 ms (typical), Sector-/Block-Erase Time: 18 ms (typical), Page-Program Time: 1.5ms (typical)
  • Packages Available: 16-lead SOIC (300 mils), 8-contact WSON (6mm x 8mm)
  • All devices are RoHS compliant
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Overview
Documents
Development Environment
Similar Devices
RoHS Information
Add To Cart

Device Overview

Summary

The SST 25 series Serial Flash family features a four-wire, SPI-compatible interface that allows for a low pin-count package which occupies less board space and ultimately lowers total system costs. SST25VF064C SPI serial flash memory is manufactured with SST proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches.


For EOL Notification, click here.
For Migration Document to SST26VF064B, click here.

Please consider this device SST26VF064B, SST26VF064BA

Additional Features
    • Serial Interface Architecture – SPI Compatible: Mode 0 and Mode 3
    • Dual Input/Output Support
    • Flexible Erase Capability: Uniform 4 KByte sectors, Uniform 32 KByte overlay blocks, Uniform 64 KByte overlay blocks
    • Low Power Consumption: Active Read Current: 12 mA (typical @ 80 MHz, Standby Current: 5 µA (typical)
    • Fast Erase and Page-Program: Chip-Erase Time: 35 ms (typical), Sector-/Block-Erase Time: 18 ms (typical), Page-Program Time: 1.5ms (typical)
    • Packages Available: 16-lead SOIC (300 mils), 8-contact WSON (6mm x 8mm)
    • All devices are RoHS compliant
Parametrics
Name
Value
Density
64 Mbit
Op. Volt Range (V)
2.7 to 3.6
Max. Clock Freq.
80 MHz
Page Size (bytes)
256
Temp Range (°C)
-40°C to +85°C
Endurance
100,000
Bus Modes
SPI

Documents

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Supporting Collateral

Board Design Files

Development Environment

  • Integrated Development Environments
  • Programmers
  • Code Examples
Integrated Development Environments
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MPLAB® X Integrated Development Environment (IDE) is an expandable, highly configurable software program that incorporates powerful tools to help you discover, configure, develop, debug and qualify embedded designs for most of Microchip’s microcontrollers, microprocessors and digital signal controllers.
MPLAB X IDE works seamlessly with the MPLAB development ecosystem of

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Programmers
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MPLAB PM3 Universal Device Programmer ( DV007004 )

The MPLAB® PM3 Universal Device Programmer is easy to use and operates with a PC or as a stand-alone unit, and programs Microchip's entire line of PIC® devices as well as the latest dsPIC® DSC devices. When used standalone, data can be loaded and saved with the SD/MMC card (not included).

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RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
SST25VF064C-80-4I-S3AE-T
0.135700
0.000000
8
SOIJ-S
.208x.284in
Matte Tin
e3
SST25VF064C-80-4I-S3AE
0.135700
0.029412
8
SOIJ-S
.208x.284in
Matte Tin
e3
SST25VF064C-80-4I-SCE
0.438000
0.765957
16
SOIC
.300In
Matte Tin
e3
SST25VF064C-80-4I-SCE-T
0.438000
0.800000
16
SOIC
.300In
Matte Tin
e3
SST25VF064C-80-4C-Q2AE
0.141500
0.716667
8
TDFN-S
6x8x0.8mm
Matte Tin
e3
SST25VF064C-80-4C-Q2AE-T
0.141500
0.250000
8
TDFN-S
6x8x0.8mm
Matte Tin
e3
SST25VF064C-80-4I-Q2AE
0.141500
0.716667
8
TDFN-S
6x8x0.8mm
Matte Tin
e3
SST25VF064C-80-4I-Q2AE-T
0.141500
0.250000
8
TDFN-S
6x8x0.8mm
Matte Tin
e3
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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