Status: In Production
The PL133-97 is an advanced fanout buffer design for high performance, low-power, small form factor applications. The PL133-97 accepts a reference clock input from DC to 150 MHz and provides 9 outputs of the same frequency.The PL133-97 is offered in a QFN-16L 3mm x 3mm package and it offers the best phase noise, additive jitter performance, and lowest power consumption of any comparable IC. The PL133-97 outputs can be disabled to a high impedance (tri-state) by pulling low the OE pin. When the OE pin is high, the outputs are enabled and follow the REF input signal. When the OE pin is left open, a pull-up resistor on the chip will default the OE pin to logic 1 so the outputs are enabled.
Development tools data is currently unavailable.
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