The LAN9215(i) is a full-featured, single-chip 10/100 Ethernet controller designed for embedded applications where performance, flexibility, ease of integration and system cost control are required. The LAN9215(i) has been architected to provide the best price-performance ratio for any 16-bit application with medium performance requirements. The LAN9215(i) is fully IEEE 802.3 10BASE-T and 802.3u 100BASE-TX compliant, and supports HP Auto-MDIX.

The LAN9215(i) includes an integrated Ethernet MAC and PHY with a high-performance SRAM-like slave interface. The simple, yet highly functional host bus interface provides a glue-less connection to most common 16-bit microprocessors and microcontrollers as well as 32-bit microprocessors with a 16-bit external bus. The LAN9215(i) includes large transmit and receive data FIFOs to accommodate high latency applications. In addition, the LAN9215(i) memory buffer architecture allows the most efficient use of memory resources by optimizing packet granularity.

The 93AA46AE48 EEPROM device from Microchip comes with a factory programmed, globally unique EUI-48™ MAC Address. This Ethernet controller will automatically detect and load the EUI-48™ node address from the 93AA46AE48 EEPROM at start-up or reset. 

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For product comparison, please consider: LAN9217, LAN9218

Highlights

• Optimized for medium performance applications
• Efficient architecture with low CPU overhead
• Easily interfaces to most 16-bit embedded CPU's
• Integrated PHY with HP Auto-MDIX Support
• Supports audio & video streaming over Ethernet: multiple standard-definition (SD) MPEG2 streams
• Compatible with other members of LAN9218 family

Target Applications

• Basic cable, satellite, and IP set-top boxes
• Digital video recorders
• Video-over IP solutions, IP PBX & video phones
• Wireless routers & access points
• Audio distribution systems
• Printers, kiosks, security systems
• General embedded applications

Key Benefits

• Non-PCI Ethernet controller for medium performance applications
  • 16-bit interface
  • Burst-mode read support
  • External MII interface
• Eliminates dropped packets
  • Internal buffer memory can store over 200 packets
  • Automatic PAUSE and back-pressure flow control
• Minimizes CPU overhead
  • Supports Slave-DMA
  • Interrupt Pin with Programmable Hold-off timer
• Reduces system cost and increases design flexibility
• SRAM-like interface easily interfaces to most Embedded CPU's or SoC's
• Reduced Power Modes
  • Numerous power management modes
  • Wake on LAN*
  • Magic packet wakeup*
  • Wakeup indicator event signal
  • Link Status Change
• Single chip Ethernet controller
  • Fully compliant with IEEE 802.3/802.3u standards
  • Integrated Ethernet MAC and PHY
  • 10BASE-T and 100BASE-TX support
  • Full- and Half-duplex support
  • Full-duplex flow control
  • Backpressure for half-duplex flow control
  • Preamble generation and removal
  • Automatic 32-bit CRC generation and checking
  • Automatic payload padding and pad removal
  • Loop-back modes
• Flexible address filtering modes
  • One 48-bit perfect address
  • 64 hash-filtered multicast addresses
  • Pass all multicast
  • Promiscuous mode
  • Inverse filtering
  • Pass all incoming with status report
  • Disable reception of broadcast packets
• Integrated 10/100 Ethernet PHY
  • Supports HP Auto-MDIX
  • Auto-negotiation
  • Supports energy-detect power down
• Host bus interface
  • Simple, SRAM-like interface
  • 16-bit data bus
  • 16Kbyte FIFO with flexible TX/RX allocation
  • One configurable host interrupt
• Miscellaneous features
  • Low-profile 100-pin TQFP, or 100-ball LFBGA (LAN9215) RoHS Compliant package
  • Integrated 1.8V regulator
  • General Purpose Timer
  • Optional EEPROM interface
  • Support for 3 status LEDs multiplexed with Programmable GPIO signals
• Single 3.3V Power Supply with 5V tolerant I/O
• Commercial and Industrial (LAN9215i) Temperature Support

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