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VESA Solutions


Arasan's VESA Display Stream Compression (DSC) IP portfolio provides standards-compliant display compression and decompression solutions for next-generation display and video systems. The portfolio includes both VESA DSC v1.2 Encoder and Decoder IP cores, enabling visually lossless compression for high-resolution display applications while reducing interface bandwidth, power consumption, memory requirements, and interconnect complexity. The IP is compliant with VESA DSC 1.2a and 1.2b specifications and supports integration into display ecosystems based on VESA Embedded DisplayPort (eDP) and MIPI DSI standards. The solution supports a wide range of RGB and YCbCr color formats, multiple bits-per-component configurations, advanced prediction algorithms, and programmable display resolutions. Optimized for low gate count, low latency, and hardware-efficient implementations, the IP can be deployed in both FPGA and ASIC designs. High-performance operation enables support for resolutions up to 8K displays while maintaining visually lossless image quality. The fully pipelined architecture facilitates efficient migration from FPGA prototypes to production ASIC implementations, making the solution suitable for high-resolution display, embedded graphics, mobile, automotive, and next-generation video applications.


Features and Benefits


  • VESA Standards Compliance
    • Fully compliant with VESA DSC 1.2a and 1.2b specifications
    • Encoder and Decoder IP implementations available
    • Supports eDP and MIPI DSI display ecosystems
  • Advanced Compression Architecture
    • Visually lossless display compression
    • Supports MMAP, BP, MPP, and ICH prediction schemes
    • Optimized display bandwidth utilization
    • Reduces frame buffer memory requirements
  • Flexible Color Format Support
    • RGB 4:4:4 support
    • YCbCr 4:4:4 support
    • YCbCr 4:2:2 support
    • YCbCr 4:2:0 support
    • Supports 8, 10, 12, 14, and 16 bits-per-component (bpc) modes
  • High-Performance Processing
    • Encoder optimized for 1 pixel/clock operation
    • Native 4:2:2 and 4:2:0 support at 2 pixels/clock
    • Decoder optimized for 3 pixels/clock operation
    • Native 4:2:2 and 4:2:0 support at 6 pixels/clock
    • Programmable display resolutions
  • Ultra-High-Resolution Display Support
    • Supports 4K display processing
    • Supports up to 8K display applications in ASIC implementations
    • Designed for UHD display systems
    • Extends resolution capabilities over existing display links

Licensing Options


For additional information , Please contact  sales@arasan.com or visit Arasan Chip Systems

Documentation


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vesa-solutions Link



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