MIPI_CSI2_Rx_decoder

MIPI_CSI2_Rx_decoder receives Camera Serial Interface 2 image traffic from a camera sensor and converts packetized sensor data into usable video outputs for FPGA-based vision systems. It fits between the MIPI physical layer and downstream image processing logic, where it removes packet framing overhead and presents pixel data with frame and line qualifiers. This core is intended for designs that need to bring mobile image sensors into a PolarFire® FPGA or PolarFire SoC FPGA without building a custom packet decoder. It handles the protocol-specific separation of short packets, long packets, payload formatting, and embedded data indication, which reduces development effort and integration risk. The architecture also supports de-multiplexing of interleaved streams by virtual channel, enabling multi-stream camera pipelines within a single receive path. Multiple output styles allow the decoded image stream to connect either to custom logic or to standard video processing subsystems. Configuration options let designers align the core to sensor format, lane arrangement, stream structure, and output packing strategy. This makes the core well suited for embedded vision, machine vision, and video capture systems that require direct MIPI CSI-2 sensor ingestion inside a programmable fabric pipeline.