The SDRAM Controller implements a controller for Single Data Rate Synchronous Dynamic Random Access Memory (SDR SDRAM) devices as specified in the JEDEC Standard No. 21-C Page 3.11.5.1 Release 12.
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Features and Benefits
- Compliant to JEDEC Standard No. 21-C Page 3.11.5.1 Release 12
- Single clock domain fully synchronous design
- Configurable to support any SDRAM device
- Very low latency: the command is issued on the clock cycle following the request
- Fully deterministic handshake interface that allows chaining of requests (read/write/terminate) to maximize bandwidth
Licensing Options
For additional information, info@safecoredevices.com or visit SafecoreDevices
Documentation
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