The CoreTSE_AHB is a Tri-Speed Ethernet Media Access Controller (MAC) designed to support 10/100/1000 Mbps Ethernet operations. It provides a bridge between a system's AMBA AHB bus and the Ethernet Physical Layer (PHY), featuring a built-in DMA engine to move data efficiently between system memory and local buffers with minimal CPU intervention. CoreTSE and CoreTSE_AHB are included in the CoreTSE_AHB license.
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Features and Benefits
- Ethernet MAC & Physical Interfaces :
- Tri- Speed support : Operates at 10 Mpbs, 100 Mbps, and 1000 Mbps
- Standard PHY Interface:
- G/MII: Gigabit Media Independent Interface for 10/100/1000 Mbps operation.
- TBI: Ten-bit Interface to support 1000BASE-X.
- Full/Half-Duplex: Supports full-duplex at all speeds and half-duplex at 10/100 Mbps.
- Data Movement & Bus IInterfaces :
- AHB Interface: Uses an AMBA AHB-initiator port for high-performance data movement.
- DMA Engine: Integrated Direct Memory Access for automated transfer between system memory and Tx/Rx FIFOs.
- Local Buffering: Internal transmit and receive FIFOs to handle data bursts and clock synchronization.
- Management & Filtering :
- Station Address Logic (SAL): Provides robust destination address filtering (Unicast, Multicast, Broadcast).
- MDIO Interface: Management Data Input/Output interface to configure and monitor the external Ethernet PHY.
- Wake-on-LAN (WoL): Detects specific "Magic Packets" to wake the system from low-power modes.
- Monitoring & Frame Handling :
- Statistics Counters: Comprehensive hardware counters for tracking transmitted/received frames and error conditions (e.g., FCS errors, alignment errors).
- Jumbo Frames: Support for oversized Ethernet frames.
- Flow Control: Implements IEEE 802.3x pause frame logic for full-duplex flow control.
- VLAN Support: Capability to handle VLAN-tagged frames.
Documentation
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| CoreTSE_AHB User Guide | Download |