CORETSE

CoreTSE is a Triple-Speed Ethernet Media Access Controller core for FPGA designs that need a complete MAC layer between system logic and an external Ethernet physical layer device. It exists to remove the effort of building and validating packet framing, media access behavior, flow control, address filtering, and management functions in custom logic. The core fits embedded networking, control-plane connectivity, and data movement paths where deterministic hardware packet handling is preferred over a software-driven MAC implementation. Its architecture combines the MAC engine with buffering, statistics collection, and optional filtering and wake features, so designers can connect application logic to Ethernet while keeping host processor load low. It also supports both parallel PHY attachment and serialized PHY attachment, which helps reuse the same networking architecture across different board designs. Optional frame screening and management capabilities simplify system integration where traffic qualification, status visibility, and PHY supervision are required inside the FPGA fabric. Configurable host-side data path selection further helps match the core to existing packet pipelines. CoreTSE delivers the most value in embedded systems that need reliable Ethernet connectivity, direct fabric access to packets, and tight integration with FPGA-based control or data processing.

Note: CoreTSE and CoreTSE_AHB are included in the CoreTSE_AHB license.