CoreSGMII

CoreSGMII is a Serial Gigabit Media Independent Interface (SGMII) IP core that provides seamless connectivity between Ethernet MACs and PHY devices through a standard SGMII interface. The core converts G/MII data streams into serial ten-bit interface (TBI) encoded symbols for transmission and performs the reverse operation on the receive path, enabling efficient Ethernet communications over FPGA-based systems. It supports Gigabit Ethernet operation at 1000 Mbps and backward compatibility with 10 Mbps and 100 Mbps Ethernet rates. CoreSGMII integrates industry-standard IEEE 802.3 Clause 37 Auto-Negotiation, allowing link partners to exchange capabilities and automatically establish the optimum operating mode. The core includes 8b/10b encoding and decoding, comma alignment, PCS error detection, and MDIO-based management and status monitoring. A dedicated ten-bit interface enables direct connectivity with FPGA transceivers and serializer/deserializer (SerDes) blocks. Designed for PolarFire®, PolarFire SoC, SmartFusion®2, IGLOO®2, and RTG4™ FPGA families, CoreSGMII provides a compact, low-resource solution for implementing Ethernet connectivity in communications, industrial, networking, aerospace, defense, and embedded system applications.