CoreRISCV_AXI4 is a softcore processor designed to implement the RISC-V instruction set for use in Microchip FPGAs. The processor is based on the Coreplex E31 designed by SiFive, containing a high-performance single-issue, in-order execution pipeline E31 32-bit RISC-V core
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Features and Benefits
- Designed for low power ASIC microcontroller and FPGA soft-core implementations.
- Integrated 8Kbytes instructions cache and 8 Kbytes data cache.
- A Platform-Level Interrupt Controller (PLIC) can support up to 31 programmable interrupt with a single priority level.
- Supports the RISCV standard RV32IM ISA.
- On-Chip debug unit with a JTAG interface.
- Two external AXI interfaces for IO and memory
Licensing Options
Free with any Libero License
Documentation
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| HB0761: CoreRISCV_AXI4 v2.0 Handbook | Download |