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Overview
The KSZ8061 32-QFN Evaluation Board is designed to enable functional and performance testing of the KSZ8061MNX PHY. In addition to the KSZ8061 PHY, there is a second PHY – a KSZ8081. The KSZ8081 is a standard 10/100 Ethernet PHY. It is used here to provide a second line interface, for simple full-duplex traffic through the KSZ8061. This board is not intended for evaluation of the KSZ8081.
Configurations include: Two-PHY MII Back-to-Back, MII Loopback and MII Connector.
- KSZ8061 PHY
- 10-Pin MDIO/MDC Header
- RXER Latch & LED
- 25MHz Clock circuit
- Reset button
- DC Power Supply
- MII Connector
- Line Connector with 3 optional configurations
- RJ-45 Connector with KSZ8081 PHY
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Documentation
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| KSZ8061MNX Windows Command Line Utility for MDC-MDIO | Board Design Files | Download | ||
| KSZ8061MNX Eval Board PADS Files | Board Design Files | Download | ||
| KSZ8061MNX Eval Board Gerber Files | Board Design Files | Download | ||
| KSZ8061MNX Eval Board BOM | Board Design Files | Download | ||
| KSZ8061MNX Eval Board Schematic | Board Design Files | Download |