The LAN9118 is a full-featured, single-chip 10/100 Ethernet controller designed for embedded applications where performance, flexibility, ease of integration and system cost control are required. The LAN9118 has been specifically architected to provide the highest performance possible for any given architecture. The LAN9118 is fully IEEE 802.3 10BASE-T and 802.3u 100BASE-TX compliant.

The LAN9118 includes an integrated Ethernet MAC and PHY with a high-performance SRAM-like slave interface. The simple, yet highly functional host bus interface provides a glue-less connection to most common 16-bit and 32-bit microprocessors and microcontrollers. LAN9118 includes large transmit and receive data FIFOs with a high-speed host bus interface to accommodate high bandwidth, high latency applications. In addition, the LAN9118 memory buffer architecture allows the most efficient use of memory resources by optimizing packet granularity.

Please consider this device LAN9218

Highlights

• Optimized for the highest-data rate applications such as high-definition video and multi-media applications
• Efficient architecture with low CPU overhead
• Easily interfaces to most 32-bit and 16-bit Embedded CPU’s
• Integrated PHY
• Supports audio & video streaming over Ethernet: multiple high-definition (HD) MPEG2 streams
• Pin compatible with other members of LAN9118 Family (LAN9117, LAN9116 and LAN9115)

Target Applications

• Video distribution systems, multi-room PVR
• High-end Cable, satellite, and IP set-top boxes
• Digital video recorders
• High definition televisions
• Digital media clients/servers
• Home gateways

Key Benefits

• Supports highest performance applications
  • Highest performing non-PCI Ethernet controller in the market
  • 32-bit interface with fast bus cycle times
  • Burst-mode read support
• Eliminates dropped packets
  • Internal buffer memory can store over 200 packets
  • Supports automatic or host-triggered PAUSE and back-pressure flow control
• Minimizes CPU overhead
  • Supports Slave-DMA
  • Interrupt Pin with Programmable Hold-off timer
• Reduces system cost and increases design flexibility
  • SRAM-like interface easily interfaces to most Embedded CPU's or SoC's
  • Low-cost, low-pin count non-PCI interface for embedded designs
• Reduced-Power Modes
  • Numerous power management modes
  • Wake on LAN*
  • Magic packet wakeup*
  • Wakeup indicator event signal
  • Link Status Change
• Single chip Ethernet controller
  • Fully compliant with IEEE 802.3/802.3u standards
  • Integrated Ethernet MAC and PHY
  • 10BASE-T and 100BASE-TX support
  • Full- and Half-duplex support
  • Full-duplex flow control
  • Backpressure for half-duplex flow control
  • Preamble generation and removal
  • Automatic 32-bit CRC generation and checking
  • Automatic payload padding and pad removal
  • Loop-back modes
• Flexible address filtering modes
  • One 48-bit perfect address
  • 64 hash-filtered multicast addresses
  • Pass all multicast
  • Promiscuous mode
  • Inverse filtering
  • Pass all incoming with status report
  • Disable reception of broadcast packets
• Integrated Ethernet PHY
  • Auto-negotiation
  • Automatic polarity detection and correction
• High-Performance host bus interface
  • Simple, SRAM-like interface
  • 32/16-bit data bus
  • Large, 16Kbyte FIFO memory that can be allocated to RX or TX functions
  • One configurable host interrupt
• Miscellaneous features
  • Low profile 100-pin, TQFP RoHS Compliant package
  • Integral 1.8V regulator
  • General Purpose Timer
  • Support for optional EEPROM
  • Support for 3 status LEDs multiplexed with Programmable GPIO signals
• 3.3V Power Supply with 5V tolerant I/O
• 0° to 70°C

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