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ECE1200

eSPI to LPC Bridge

Status: In Production

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Device Overview

Summary

The ECE1200 is a device designed to implement a Bridge function from an eSPI-configured Intel Chipset to a legacy downstream system, providing Master interfaces for an LPC bus, Serial IRQ and CLKRUN# features.

The ECE1200 is directly powered by two Suspend (S5) supply planes, at 3.3V and 1.8V nominal. The 1.8V supply is provided on two sets of pins: VTR_18 for I/O pins, and VTR_18_CORE for internal logic. The 3.3V supply VTR_33 is for 3.3V I/O pins only.

The ECE1200 senses a Runtime power plane (VCC) using the pin LPC_EN, which is intended to come from the PCH_PWROK signal supplied from the system. It uses this to emulate VCC-powered functionality on the appropriate pins in order to avoid backdrive in the system.

Additional Features
  • Detects and Supports Modern Standby State
  • ACPI 6.1 Compliant
  • Supports LPC-based SIO and EC devices such as SCH311x, SCH322x
  • eSPI Peripheral Channel Cycles in 64K I/O Space will pass through as LPC I/O cycles, except for the local Plug-and-Play INDEX/DATA portal registers
  • 40-pin VQFN package
  • Industrial Temperature Range: -40°C to +85°C

Documents

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Data Sheet

05/30/2019
946KB

Errata

06/03/2019
80KB

Development tools data is currently unavailable.

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RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
ECE1200-I/LD
0.740816
40
VQFN
5x5x0.9mm
Matte Tin
e3
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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