Microchip Technology Inc
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dsPIC33FJ128GP802

Status: In Production

Features:

  • Industrial temperature range (-40°C to +85°C)
  • Extended temperature range (-40°C to +125°C)
  • Modified Harvard architecture
  • C compiler optimized instruction set
  • 16-bit wide data path
  • 24-bit wide instructions
  • Linear program memory addressing up to 4M instruction words
  • Linear data memory addressing up to 64 Kbytes
  • 83 base instructions: mostly 1 word/1 cycle
  • Two 40-bit accumulators with rounding and saturation options
  • Indirect
  • Modulo
  • Bit-Reversed
  • Software stack
  • 16 x 16 fractional/integer multiply operations
  • 32/16 and 16/16 divide operations
  • Accumulator write back for DSP operations
  • Dual data fetch
  • Up to ±16-bit shifts for up to 40-bit data
  • Flash program memory
  • Data SRAM
  • Boot, Secure, and General Security for program Flash
  • 8-channel hardware DMA
  • Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing)
  • Most peripherals support DMA
  • Can pair up to make two 32-bit timers
  • One timer runs as a Real-Time Clock with an external 32.768 kHz oscillator
  • Programmable prescaler
  • Capture on up, down or both edges
  • 16-bit capture input functions
  • 4-deep FIFO on each capture
  • Single or Dual 16-bit Compare mode
  • 16-bit Glitchless PWM mode
  • Provides clock, calendar, and alarm functions
  • 5-cycle latency
  • 118 interrupt vectors
  • Up to 49 available interrupt sources
  • Up to three external interrupts
  • Seven programmable priority levels
  • Five processor exceptions
  • Peripheral pin Select functionality
  • Up to 35 programmable digital I/O pins
  • Wake-up/Interrupt-on-Change for up to 21 pins
  • Output pins can drive from 3.0V to 3.6V
  • Up to 5V output with open drain configuration
  • All digital input pins are 5V tolerant
  • 4 mA sink on all I/O pins
  • External, crystal, resonator, internal RC
  • Fully integrated Phase-Locked Loop (PLL)
  • Extremely low jitter PLL
  • Power-up Timer
  • Oscillator Start-up Timer/Stabilizer
  • Watchdog Timer with its own RC oscillator
  • Fail-Safe Clock Monitor
  • Reset by multiple sources
  • On-chip 2.5V voltage regulator
  • Switch between clock sources in real time
  • Idle, Sleep, and Doze modes with fast wake-up
  • Two and four simultaneous samples (10-bit ADC)
  • Up to 13 input channels with auto-scanning
  • Conversion start can be manual or synchronized with one of four trigger sources
  • Conversion possible in Sleep mode
  • ±2 LSb max integral nonlinearity
  • ±1 LSb max differential nonlinearity
  • 16-bit Dual Channel DAC module
  • 100 Ksps maximum sampling rate
  • Second-Order Digital Delta-Sigma Modulator
  • Codec interface
  • Supports I2S and AC.97 protocols
  • Up to 16-bit data words, up to 16 words per frame
  • 4-word deep TX and RX buffers
  • Two analog comparators with programmable input/output configuration
  • Low-power, high-speed Flash technology
  • Fully static design
  • 3.3V (±10%) operating voltage
  • Industrial and Extended temperature
  • Low power consumption
  • Framing supports I/O interface to simple codecs
  • Supports 8-bit and 16-bit data
  • Supports all serial clock formats and sampling modes
  • Full Multi-Master Slave mode support
  • 7-bit and 10-bit addressing
  • Bus collision detection and arbitration
  • Integrated signal conditioning
  • Slave address masking
  • Interrupt on address bit detect
  • Interrupt on UART error
  • Wake-up on Start bit from Sleep mode
  • 4-character TX and RX FIFO buffers
  • LIN bus support
  • IrDA® encoding and decoding in hardware
  • High-Speed Baud mode
  • Hardware Flow Control with CTS and RTS
  • Enhanced CAN (ECAN. module) 2.0B active:
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Overview
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Development Environment
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Device Overview

Additional Features

    Operating Range:

    • Up to 40 MIPS operation (at 3.0-3.6V):
      • Industrial temperature range (-40°C to +85°C)
      • Extended temperature range (-40°C to +125°C)

    High-Performance DSC CPU:

    • Modified Harvard architecture
    • C compiler optimized instruction set
    • 16-bit wide data path
    • 24-bit wide instructions
    • Linear program memory addressing up to 4M instruction words
    • Linear data memory addressing up to 64 Kbytes
    • 83 base instructions: mostly 1 word/1 cycle
    • Two 40-bit accumulators with rounding and saturation options
    • Flexible and powerful addressing modes:
      • Indirect
      • Modulo
      • Bit-Reversed
    • Software stack
    • 16 x 16 fractional/integer multiply operations
    • 32/16 and 16/16 divide operations
    • Single-cycle multiply and accumulate:
      • Accumulator write back for DSP operations
      • Dual data fetch
    • Up to ±16-bit shifts for up to 40-bit data

    On-Chip Flash and SRAM:

    • Flash program memory
    • Data SRAM
    • Boot, Secure, and General Security for program Flash

    Direct Memory Access (DMA):

    • 8-channel hardware DMA
    • Up to 2 Kbytes dual ported DMA buffer area (DMA RAM) to store data transferred via DMA:
      • Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing)
    • Most peripherals support DMA

    Timers/Capture/Compare/PWM:

    • Timer/Counters, up to five 16-bit timers:
      • Can pair up to make two 32-bit timers
      • One timer runs as a Real-Time Clock with an external 32.768 kHz oscillator
      • Programmable prescaler
    • Input Capture (up to four channels):
      • Capture on up, down or both edges
      • 16-bit capture input functions
      • 4-deep FIFO on each capture
    • Output Compare (up to four channels):
      • Single or Dual 16-bit Compare mode
      • 16-bit Glitchless PWM mode
    • Hardware Real-Time Clock/Calendar (RTCC):
      • Provides clock, calendar, and alarm functions

    Interrupt Controller:

    • 5-cycle latency
    • 118 interrupt vectors
    • Up to 49 available interrupt sources
    • Up to three external interrupts
    • Seven programmable priority levels
    • Five processor exceptions

    Digital I/O:

    • Peripheral pin Select functionality
    • Up to 35 programmable digital I/O pins
    • Wake-up/Interrupt-on-Change for up to 21 pins
    • Output pins can drive from 3.0V to 3.6V
    • Up to 5V output with open drain configuration
    • All digital input pins are 5V tolerant
    • 4 mA sink on all I/O pins

    System Management:

    • Flexible clock options:
      • External, crystal, resonator, internal RC
      • Fully integrated Phase-Locked Loop (PLL)
      • Extremely low jitter PLL
    • Power-up Timer
    • Oscillator Start-up Timer/Stabilizer
    • Watchdog Timer with its own RC oscillator
    • Fail-Safe Clock Monitor
    • Reset by multiple sources

    Power Management:

    • On-chip 2.5V voltage regulator
    • Switch between clock sources in real time
    • Idle, Sleep, and Doze modes with fast wake-up

    Analog-to-Digital Converters (ADCs):

    • 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion:
      • Two and four simultaneous samples (10-bit ADC)
      • Up to 13 input channels with auto-scanning
      • Conversion start can be manual or synchronized with one of four trigger sources
      • Conversion possible in Sleep mode
      • ±2 LSb max integral nonlinearity
      • ±1 LSb max differential nonlinearity

    Audio Digital-to-Analog Converter (DAC):

    • 16-bit Dual Channel DAC module
    • 100 Ksps maximum sampling rate
    • Second-Order Digital Delta-Sigma Modulator

    Data Converter Interface (DCI) module:

    • Codec interface
    • Supports I2S and AC.97 protocols
    • Up to 16-bit data words, up to 16 words per frame
    • 4-word deep TX and RX buffers

    Comparator Module:

    • Two analog comparators with programmable input/output configuration

    CMOS Flash Technology:

    • Low-power, high-speed Flash technology
    • Fully static design
    • 3.3V (±10%) operating voltage
    • Industrial and Extended temperature
    • Low power consumption

    Communication Modules:

    • 4-wire SPI (up to two modules):
      • Framing supports I/O interface to simple codecs
      • Supports 8-bit and 16-bit data
      • Supports all serial clock formats and sampling modes
    • I2C™:
      • Full Multi-Master Slave mode support
      • 7-bit and 10-bit addressing
      • Bus collision detection and arbitration
      • Integrated signal conditioning
      • Slave address masking
    • UART (up to two modules):
      • Interrupt on address bit detect
      • Interrupt on UART error
      • Wake-up on Start bit from Sleep mode
      • 4-character TX and RX FIFO buffers
      • LIN bus support
      • IrDA® encoding and decoding in hardware
      • High-Speed Baud mode
      • Hardware Flow Control with CTS and RTS
    • Enhanced CAN (ECAN. module) 2.0B active:
    Parametrics
    Name
    Value
    Architecture
    16-bit
    Max CPU Speed (MHz)
    40
    CPU Speed (MIPS/DMIPS)
    40
    Program Memory Size (KB)
    128
    SRAM (KB)
    16
    Direct Memory Access Channels
    8
    Temperature Range (C)
    -40 to 125
    Operating Voltage Range (V)
    3 to 3.6
    Pin Count
    28
    Comparators
    2
    Analog Peripherals
    1-A/D 10x12-bit @ 1100(ksps) 2-D/A 2x16-bit
    UART
    2
    SPI
    2
    I2C
    1
    Timers
    5 x 16-bit 2 x 32-bit
    Input Capture
    4
    Max PWM outputs (including complementary)
    4
    Number of PWM Time Bases
    2
    Output Compare Channels
    4
    Number of CAN Modules
    1
    Type of CAN Module
    CAN
    Class B Hardware
    Yes
    Peripheral Pin Select / Pin Muxing
    Yes

    Documents

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    Programming Specifications

    Reference Manual

    Download All
    03/18/2014
    668KB
    03/14/2014
    467KB

    Software

    Boundary Scan BSDL

    10/12/2012
    8KB

    Code Examples

    12/10/2009
    34KB
    08/17/2009
    20KB
    08/17/2009
    31KB
    08/17/2009
    13KB
    12/10/2009
    45KB
    08/17/2009
    16KB
    12/10/2009
    24KB
    08/17/2009
    12KB
    10/24/2013
    49KB

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    • Socket: AC164337   PartNo: DSPIC33FJ128GP802 (28SP)
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    RoHS Information

    Part Number
    Device Weight
    Shipping Weight
    Lead Count
    Package Type
    Package Width
    Solder Composition
    JEDEC Indicator
    RoHS
    China EFUP
    DSPIC33FJ128GP802T-I/SO
    0.770400
    1.152500
    28
    SOIC
    .300in
    Matte Tin
    e3
    Rohs icon
    efup china icon
    DSPIC33FJ128GP802-I/SO
    0.770400
    1.370370
    28
    SOIC
    .300in
    Matte Tin
    e3
    Rohs icon
    efup china icon
    DSPIC33FJ128GP802T-E/SO
    0.770400
    1.152500
    28
    SOIC
    .300in
    Matte Tin
    e3
    Rohs icon
    efup china icon
    DSPIC33FJ128GP802-E/SO
    0.770400
    1.370370
    28
    SOIC
    .300in
    Matte Tin
    e3
    Rohs icon
    efup china icon
    DSPIC33FJ128GP802-E/SP
    2.087500
    3.733333
    28
    SPDIP
    .300in
    Matte Tin
    e3
    Rohs icon
    efup china icon
    DSPIC33FJ128GP802-I/SP
    2.087500
    3.733333
    28
    SPDIP
    .300in
    Matte Tin
    e3
    Rohs icon
    efup china icon
    DSPIC33FJ128GP802T-I/MM
    0.101600
    0.418750
    28
    QFN-S
    6x6x0.9mm
    Matte Tin
    e3
    Rohs icon
    efup china icon
    DSPIC33FJ128GP802-E/MM
    0.101600
    0.163934
    28
    QFN-S
    6x6x0.9mm
    Matte Tin
    e3
    Rohs icon
    efup china icon
    DSPIC33FJ128GP802-I/MM
    0.101600
    0.163934
    28
    QFN-S
    6x6x0.9mm
    Matte Tin
    e3
    Rohs icon
    efup china icon
    DSPIC33FJ128GP802T-E/MM
    0.101600
    0.418750
    28
    QFN-S
    6x6x0.9mm
    Matte Tin
    e3
    Rohs icon
    efup china icon
    To see a complete listing of RoHS data for this device, please Click here
    Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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