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dsPIC33FJ12GP202

Status: In Production

Features:

  • Up to 40 MIPS operation (at 3.0-3.6V)
  • Extended temperature range (-40°C to +125°C)
  • Single-cycle MAC with accumulator write back for DSP operations and dual data fetch
  • On-chip 2.5V voltage regulator
  • ADC with 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion
  • Two and four simultaneous samples (10-bit ADC)
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Overview
Documents
Development Environment
Similar Devices
RoHS Information
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Device Overview

Summary

 •dsPIC33Fs are designed to execute digital filter algorithms and high-speed precision digital control loops, ideal for applications that need to perform under pressure           •General Purpose Digital Signal Controllers (DSCs) with advanced analog and seamless migration options to PIC24F, PIC24H MCUs and dsPIC30F DSCs 

Additional Features
  • Operating Range
    • Up to 40 MIPS operation (at 3.0-3.6V)
    • Industrial temperature range (-40°C to +85°C)
    • Extended temperature range (-40°C to +125°C)
  • High-Performance dsPIC33F core
    • Modified Harvard architecture
    • C compiler optimized instruction set
    • 16-bit wide data path, 24-bit wide instructions
    • Linear program memory addressing up to 4M instruction words
    • Linear data memory addressing up to 64 Kbytes
    • 83 base instructions, mostly one word/one cycle
    • Sixteen 16-bit general purpose registers
    • Two 40-bit accumulators with rounding and saturation options
    • Flexible and powerful addressing modes: - Indirect - Modulo - Bit-Reversed
    • Software stack
    • 16 x 16 fractional/integer multiply operations
    • 32/16 and 16/16 divide operations
    • Single-cycle MAC with accumulator write back for DSP operations and dual data fetch
    • Up to ±16-bit shifts for up to 40-bit data
  • Interrupt Controller
    • 5-cycle latency
    • Up to 21 available interrupt sources
    • Up to three external interrupts
    • Seven programmable priority levels
    • Four processor exceptions
  • On-Chip Flash and SRAM
    • Flash program memory (12 Kbytes)
    • Data SRAM (1024 bytes)
    • Boot and General Security for Program Flash
  • Digital I/O
    • Peripheral Pin Select Functionality
    • Up to 21 programmable digital I/O pins
    • Wake-up/interrupt-on-change for up to 21 pins
    • Output pins can drive from 3.0V to 3.6V
    • Up to 5V output with open drain configurations on 5V tolerant pins
    • 4 mA sink on all I/O pins
  • System Management
    • Flexible clock options: - External, crystal, resonator, internal RC - Fully Integrated Phase-Locked Loop (PLL) - Extremely low-jitter PLL
    • Power-up Timer
    • Oscillator Start-up Timer/Stabilizer
    • Watchdog Timer with its own RC oscillator
    • Fail-Safe Clock Monitor
  • Power Management
    • On-chip 2.5V voltage regulator
    • Switch between clock sources in real time
    • Idle, Sleep and Doze modes with fast wake-up
  • Timers/Capture/Compare
    • Up to three 16-bit timers which can pair up to make one 32-bit timer
    • Input Capture (up to four channels): - Capture on up, down, or both edges
    • 16-bit capture input functions, 4-deep FIFO on each capture
    • Output Compare (up to two channels) with Single or Dual 16-bit Compare mode
  • Communication Modules
    • 4-wire SPI: - Framing supports I/O interface to simple codecs, supports 8-bit and 16-bit data and supports all serial clock formats and sampling modes
    • I2C™: - Full Multi-Master Slave mode support, 7-bit and 10-bit addressing, bus collision detection and arbitration, slave address masking and integrated signal conditioning
    • UART: - Provides LIN bus support, IrDA® encoding and decoding in hardware, High-Speed Baud Mode and Hardware Flow Control with CTS and RTS
  • Analog-to-Digital Converters (ADCs)
    • ADC with 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion
    • Two and four simultaneous samples (10-bit ADC)
    • Up to 10 input channels with auto-scanning
    • Conversion start can be manual or synchronized with one of four trigger sources
    • Conversion possible in Sleep mode
    • ±2 LSb max integral nonlinearity
    • ±1 LSb max differential nonlinearity
  • Packaging
    • 18-pin PDIP/SOIC
    • 28-pin SPDIP/SOIC/SSOP/QFN
Parametrics
Name
Value
Architecture
16-bit
Max CPU Speed (MHz)
40
CPU Speed (MIPS/DMIPS)
40
Program Memory Size (KB)
12
SRAM (KB)
1
Temperature Range (C)
-40 to 125
Operating Voltage Range (V)
3 to 3.6
Pin Count
28
Analog Peripherals
1-A/D 10x12-bit @ 1100(ksps)
UART
1
SPI
1
I2C
1
Timers
3 x 16-bit 1 x 32-bit
Input Capture
4
Max PWM outputs (including complementary)
2
Number of PWM Time Bases
2
Output Compare Channels
4
Class B Hardware
Yes
Peripheral Pin Select / Pin Muxing
Yes

Documents

Jump to:

Data Sheet

Programming Specification

BSDL Files

Code Examples

12/10/2009
34KB
08/17/2009
20KB
08/17/2009
31KB
08/17/2009
13KB
12/10/2009
45KB
08/17/2009
16KB
12/10/2009
24KB
08/17/2009
12KB
10/24/2013
49KB

Product Document

Brochures

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Development Environment

  • Demo & Evaluation Boards
  • Emulators & Debuggers
  • Programmers
  • Software Libraries
  • Code Examples
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Explorer 16/32 Development Board
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Emulators & Debuggers
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Debug Features:
Runtime watch:Supported
Native Trace:True
I/O Port Trace:True (Requires Compiler Support)
SPI Trace:True (Requires Compiler Support)


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Programmers
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  • Socket: AC164337   PartNo: DSPIC33FJ12GP202 (28SP)
  • Socket: AC164339   PartNo: DSPIC33FJ12GP202 (28SO)
  • Socket: AC164336   PartNo: DSPIC33FJ12GP202 (28ML)
  • Socket: AC164338   PartNo: DSPIC33FJ12GP202 (28SS)
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MPLAB ICD 3 In-Circuit Debugger
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Software Libraries
16-bit CPU Self-test Library

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Code Examples

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RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
DSPIC33FJ12GP202T-E/SO
0.770400
1.152500
28
SOIC
.300in
Matte Tin
e3
DSPIC33FJ12GP202-E/SO
0.770400
1.370370
28
SOIC
.300in
Matte Tin
e3
DSPIC33FJ12GP202T-I/SO
0.770400
1.152500
28
SOIC
.300in
Matte Tin
e3
DSPIC33FJ12GP202-I/SO
0.770400
1.370370
28
SOIC
.300in
Matte Tin
e3
DSPIC33FJ12GP202-E/SP
2.087500
3.733333
28
SPDIP
.300in
Matte Tin
e3
DSPIC33FJ12GP202-I/SP
2.087500
3.733333
28
SPDIP
.300in
Matte Tin
e3
DSPIC33FJ12GP202-E/ML
0.101600
0.163934
28
QFN
6x6x0.9mm
Matte Tin
e3
DSPIC33FJ12GP202T-E/ML
0.101600
0.332500
28
QFN
6x6x0.9mm
Matte Tin
e3
DSPIC33FJ12GP202T-I/ML
0.101600
0.332500
28
QFN
6x6x0.9mm
Matte Tin
e3
DSPIC33FJ12GP202-I/ML
0.101600
0.163934
28
QFN
6x6x0.9mm
Matte Tin
e3
DSPIC33FJ12GP202T-E/SS
0.229200
0.333333
28
SSOP
.209in
Matte Tin
e3
DSPIC33FJ12GP202-I/SS
0.229200
0.489362
28
SSOP
.209in
Matte Tin
e3
DSPIC33FJ12GP202T-I/SS
0.229200
0.333333
28
SSOP
.209in
Matte Tin
e3
DSPIC33FJ12GP202-E/SS
0.229200
0.489362
28
SSOP
.209in
Matte Tin
e3
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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