The ZL40260 is a 2x10 LVPECL clock fan out buffer with ten identical output clock drivers capable of operating at frequencies up to 1600MHz. The ZL40260 has two inputs. Each input can accept differential (LVPECL, SSTL, LVDS, HSTL, CML) or a single ended LVPECL input or a CMOS input. The voltage level at CLK_SEL pin selects which input will be passed to the output drivers. LVPECL input must be externally biased and terminated with resistors. The device provides biasing voltage at the output pin Vbb which can minimize number of external resistors.
The ZL40260 is designed to fan out low-jitter reference clocks for wired or optical communications applications while adding minimal jitter to the clock signal. An internal linear power supply regulator and bulk capacitors minimize additive jitter due to power supply noise. The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its operation is guaranteed over the industrial temperature range -40°C to +85°C.
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