Microchip logo
  • All
  • Products
  • Documents
  • Applications Notes
product primary image

ZL40260

2:10 Low Skew/Low Jitter LVPECL Buffer

Status: In Production

View More
Overview
Documents
Development Environment
RoHS Information
Add To Cart

Device Overview

Summary

The ZL40260 is a 2x10 LVPECL clock fan out buffer with ten identical output clock drivers capable of operating at frequencies up to 1600MHz. The ZL40260 has two inputs. Each input can accept differential (LVPECL, SSTL, LVDS, HSTL, CML) or a single ended LVPECL input or a CMOS input. The voltage level at CLK_SEL pin selects which input will be passed to the output drivers. LVPECL input must be externally biased and terminated with resistors. The device provides biasing voltage at the output pin Vbb which can minimize number of external resistors.

The ZL40260 is designed to fan out low-jitter reference clocks for wired or optical communications applications while adding minimal jitter to the clock signal. An internal linear power supply regulator and bulk capacitors minimize additive jitter due to power supply noise. The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its operation is guaranteed over the industrial temperature range -40°C to +85°C.

Additional Features
  • Two inputs accept any differential (LVPECL, HCSL, LVDS, SSTL, CML) or single ended LVCMOS signal
  • Ten 2.5V/3.3V LVPECL outputs
  • Ultra-low additive jitter: 53fs for 125 MHz clock measured in 12KHz to 20MHz band
  • Supports clock frequencies from 0 to 1.6GHz
  • Supports 2.5V or 3.3V power supplies
  • Embedded Low Drop Out (LDO) Voltage regulator provides superior Power Supply Noise Rejection
  • Maximum output to output skew of 50ps
  • Maximum input to output delay of 1.2ns
  • Small input to output delay variation over voltage, temperature and process of 0.34ns
  • Fast rise and fall times of 168ps
  • Phase noise floor below -160dB/Hz for 125MHz clock
Parametrics
Name
Value
Product Type
Fanout & Buffer and Drivers
Description
Fanout Buffer
Input
LVPECL/HCSL/LVDS/SSTL/CML/LVCMOS
Output
LVPECL
Supply Voltage
2.5/3.3
Max Freq (GHz)
1.6
Max Prop Delay (ps)
1186
Max Within Device Skew (ps)
50
OE
False
RPE
False
FSI
False
Input Mux
True
Input EQ
False
Output Type
LVPECL
Number Of Outputs
10

Documents

Jump to:

Data Sheets

  
806KB

Application Notes


Development tools data is currently unavailable.

RoHS Information

Part Number
Device Weight (g)
Shipping Weight (grams)
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
ZL40260QGF1
0.147200
0.440000
32
TQFP
7x7x1.0mm
Matte Tin
e3
ZL40260QGG1
0.147200
0.150000
32
TQFP
7x7x1.0mm
Matte Tin
e3
ZL40260LDF1
0.067400
0.150000
32
VQFN
5x5x1mm
Matte Tin
e3
ZL40260LDG1
0.067400
0.150000
32
VQFN
5x5x1mm
Matte Tin
e3
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

Buy from Microchip

Grid
View
Table
View
Filter:
Apply
Clear
Only show products with samples
Product
Leads
Package Type
Temp Range
Packing Media
5K Pricing
Buy