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ZL30101

PDH System Synchronizer

Status: In Production

Features:

  • Supports Telcordia GR-1244-CORE Stratum 3
  • Supports G.823 and G.824 for 2048 kbps and 1544 kbps interfaces
  • Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces
  • Simple hardware control interface
  • Accepts two input references and synchronizes to any combination of 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz or 16.384 MHz inputs
  • Provides a range of clock outputs: 1.544 MHz, 2.048 MHz, 16.384 MHz and either 4.096 MHz and 8.192 MHz or 32.768 MHz and 65.536 MHz
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

The ZL30101 Stratum 3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk T1 and E1 transmission equipment.
The ZL30101 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of two input references. It helps ensure system reliability by monitoring its references for accuracy and stability and by maintaining stable output clocks during reference switching operations and during short periods when a reference is unavailable.
The ZL30101 is intended to be the central timing and synchronization resource for network equipment that complies with Telcordia, ETSI, ITU-T and ANSI network specifications.

Additional Features
  • Supports Telcordia GR-1244-CORE Stratum 3
  • Supports G.823 and G.824 for 2048 kbps and 1544 kbps interfaces
  • Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces
  • Simple hardware control interface
  • Accepts two input references and synchronizes to any combination of 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz or 16.384 MHz inputs
  • Provides a range of clock outputs: 1.544 MHz, 2.048 MHz, 16.384 MHz and either 4.096 MHz and 8.192 MHz or 32.768 MHz and 65.536 MHz
  • Provides 5 styles of 8 kHz framing pulses
  • Holdover frequency accuracy of 1 x 10-8
  • Lock, Holdover and Out of Range indication
  • Selectable loop filter bandwidth of 1.8 Hz or 922 Hz
  • Less than 0.5 nspp jitter on all output clocks
  • External master clock source: clock oscillator or crystal
Parametrics
Name
Value
Type
PDH/SDH
DPLLs or Paths
1
DPLL Bandwidth (Hz)
1.8 Hz or 922 Hz
Inputs
2
CMOS Outputs
5
Typical Jitter (12kHz-20MHz) fs RMS
PDH Interfaces
Diff InputFreq Range
8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz or 16.384 MHz
Output Freq Range
65.536 MHz
NV Memory
N/A
NCO ppb
N/A
Align
3

Documents

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Data Sheets

  
421KB

Development tools data is currently unavailable.

RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Dimension
Solder Composition
JEDEC Indicator
RoHS
China EFUP
ZL30101QDG1
0.286700
2.562500
64
TQFP
10x10x1mm
Matte Tin
e3
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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