Microsemi's proven Gigabit PHY technology is available for integration in Ethernet ASIC and ASSP platforms. Microsemi Corporation, a leading provider of physical layer technology, has deployed over 250 million Gigabit Ethernet PHY ports into various production platforms across the globe. Now, Microsemi PHY core integration enables systems to achieve lower system Bill of Material (BOM) costs compared to standalone PHY products, making systems less expensive to produce and more cost effective to deploy. The mixed-signal IP core provides 10/100/1000BASE-T PHY functions with support for IEEE 802.3az Energy Efficient Ethernet (EEE), Wake-on-LAN (WoL), Synchronous Ethernet (SyncE) physical layer timing recovery, Start of Frame (SOF), and Fast Link Failure 2.0 (FLF2) indication. Ideal for emerging green applications, the IP core supports Microsemi's EcoEthernet™ 2.0 power-saving features including the PerfectReach™ intelligent cable length algorithm, which saves power based on the reach of a connection, and ActiPHY™, which provides power savings of over 75% for ports with no link.
Documentation data is currently unavailable.
Development tools data is currently unavailable.
Rohs data is currently unavailable.
For pricing and availability, contact Microchip Local Sales.