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VSC9908

Test Chip: 9908-01 40LP 2p GE PHY core

Status: Samples Available

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Device Overview

Summary

Microsemi's proven Gigabit PHY technology is available for integration in Ethernet ASIC and ASSP platforms. Microsemi Corporation, a leading provider of physical layer technology, has deployed over 250 million Gigabit Ethernet PHY ports into various production platforms across the globe. Now, Microsemi PHY core integration enables systems to achieve lower system Bill of Material (BOM) costs compared to standalone PHY products, making systems less expensive to produce and more cost effective to deploy. The mixed-signal IP core provides 10/100/1000BASE-T PHY functions with support for IEEE 802.3az Energy Efficient Ethernet (EEE), Wake-on-LAN (WoL), Synchronous Ethernet (SyncE) physical layer timing recovery, Start of Frame (SOF), and Fast Link Failure 2.0 (FLF2) indication. Ideal for emerging green applications, the IP core supports Microsemi's EcoEthernet™ 2.0 power-saving features including the PerfectReach™ intelligent cable length algorithm, which saves power based on the reach of a connection, and ActiPHY™, which provides power savings of over 75% for ports with no link.

Additional Features
  • FEC Cores
    • FEC Cores
    • GE Switch Cores
    • GE PHY hard macro for TSMC 40LP
    • IEEE 802.3-2008 compliant with IEEE 802.3az energy efficiency
    • Lowest BOM solution using only two voltage planes
    • Robust EMI and ESD performance
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Clock and Data Recovery

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