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SY89871UMG

Status: In Production

Features:

  • Bank A: undivided pass-through (QA)
  • Bank B: programmable divide by 2, 4, 8, 16 (QB0, QB1)
  • Matched delay: all outputs have matched delay, independent of divider setting
  • >2.5GHz fMAX
  • <250ps tr/tf
  • <670ps tpd (matched delay)
  • <15ps within-device skew
  • 231fsRMS phase jitter (typ.)
  • Power supply 3.3V or 2.5V
  • Unique patent-pending input termination and VT pin for DC- and AC-coupled inputs: any differential inputs (LVPECL, LVDS, CML, HSTL)
  • TTL/CMOS inputs for select and reset
  • 100K EP compatible LVPECL outputs
  • Parallel programming capability
  • Wide operating temperature range: -40°C to +85°C
  • Available in 16-pin (3mm x 3mm) QFN package
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

The SY89871UMG is a 2.5V/3.3V LVPECL output precision clock divider capable of accepting a high-speed differential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS clock input signal and dividing down the frequency using a programmable divider ratio to create a frequency locked lower speed version of the input clock (Bank B).Available divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, 77MHz, or 38MHz auxiliary clock components.

The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF-AC reference is included for AC-coupled applications.The SY89871U includes two phase-matched output banks. Bank A (QA) is a frequency-matched copy of the input. Bank B (QB0, QB1) is a divided down output of the input frequency. Bank A and Bank B maintain a matched delay independent of the divider setting.

Additional Features
    • Two matched-delay outputs:
      • Bank A: undivided pass-through (QA)
      • Bank B: programmable divide by 2, 4, 8, 16 (QB0, QB1)
    • Matched delay: all outputs have matched delay, independent of divider setting
    • Guaranteed AC performance:
      • >2.5GHz fMAX
      • <250ps tr/tf
      • <670ps tpd (matched delay)
      • <15ps within-device skew
    • Low jitter design
      • 231fsRMS phase jitter (typ.)
    • Power supply 3.3V or 2.5V
    • Unique patent-pending input termination and VT pin for DC- and AC-coupled inputs: any differential inputs (LVPECL, LVDS, CML, HSTL)
    • TTL/CMOS inputs for select and reset
    • 100K EP compatible LVPECL outputs
    • Parallel programming capability
    • Wide operating temperature range: -40°C to +85°C
    • Available in 16-pin (3mm x 3mm) QFN package
Parametrics
Name
Value
Product Type
Divider
Input
ANY
Supply Voltage
2.5/3.3
Max Prop Delay (ps)
670
Max Within Device Skew (ps)
15
OE
False
RPE
False
FSI
False
Input Mux
False
Input EQ
False
Output Type
LVPECL

Documents

Jump to:

Data Sheet

04/30/2018
710KB

User Guides

11/11/2015
143KB

Development tools data is currently unavailable.

RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
SY89871UMG-TR
0.021300
0.801700
16
VQFN
3x3x1.00mm
NiPdAu
e4
SY89871UMG
0.021300
0.050000
16
VQFN
3x3x1.00mm
NiPdAu
e4
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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