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SY89808L

Status: Not Recommended for new designs

Features:

  • 9 differential HSTL (1.5V compatible) output pairs
  • 500MHz maximum clock frequency
  • Triple-buffered enable function
  • 3.3V core supply, 1.8V output supply for reduced power
  • LVPECL and HSTL inputs
  • HSTL outputs drive 50Ω to ground with no offset voltage
  • Low pin-to-pin skew (25ps max.)
  • Guaranteed over industrial -40°C to +85°C temperature range
  • Available in 32-pin TQFP package
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Device Overview

Summary

The SY89808L is a High-Performance Bus Clock Driver with 9 differential HSTL (High-Speed Transceiver Logic) 1.5V compatible output pairs. The part is designed for use in lowvoltage (3.3V/1.8V) applications which require a large number of outputs to drive precisely aligned, ultra-low skew signals to their destination. The input is multiplexed from either HSTL or LVPECL (Low-Voltage Positive-Emitter-Coupled Logic) by the CLK_SEL pin.The Output Enable (OE) is synchronous and triple-buffered so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any potential of generating a runt clock pulse when the device is enabled/disabled, as can occur with an asynchronous control. The triple-buffering feature provides a three-clock delay from the time the OE input is asserted/de-asserted to when the clock appears at the outputs.The SY89808L features an ultra-low pin-to-pin skew of less than 25ps. The SY89808L is available in a 32-TQFP space saving package, enabling a lower overall cost solution.

Additional Features
    • 9 differential HSTL (1.5V compatible) output pairs
    • 500MHz maximum clock frequency
    • Triple-buffered enable function
    • 3.3V core supply, 1.8V output supply for reduced power
    • LVPECL and HSTL inputs
    • HSTL outputs drive 50Ω to ground with no offset voltage
    • Low pin-to-pin skew (25ps max.)
    • Guaranteed over industrial -40°C to +85°C temperature range
    • Available in 32-pin TQFP package
Parametrics
Name
Value
Product Type
Fanout & Buffer and Drivers
Description
2:9
Input
LVPECL/HSTL
Output
HSTL
Supply Voltage
3.3V
Max Freq (GHz)
0.5
Max Prop Delay (ps)
<1200
Icc (mA)
80
Max Within Device Skew (ps)
<400
OE
True
RPE
False
FSI
False
Input Mux
True
Input EQ
False

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