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SY89534L

Status: Not Recommended for new designs

Features:

  • Integrated synthesizer plus fanout buffers, clock dividers, and translator in a single 64-pin package
  • Accepts any reference input between 14MHz to 160MHz (single-ended or differential)
  • 33MHz to 500MHz output frequency range
  • LVPECL outputs (SY89534L)
  • LVPECL and LVDS outputs (SY89535L)
  • 3.3V ±10% power supply
  • Low jitter: <50ps cycle-to-cycle
  • Low pin-to-pin skew: <50ps
  • TTL/CMOS compatible control logic
  • 9 differential output pairs @BankB (LVPECL/LVDS)
  • 2 differential output pairs @BankA (LVPECL)
  • 2 differential output pairs @BankC (LVPECL)
  • Available in 64-pin EPAD-TQFP
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Device Overview

Summary

The SY89534L and SY89535L programmable clock synthesizers are a 3.3V, high-frequency, precision PLL-based family optimized for multi-frequency, large clock-tree applications that require the highest precision. These devices integrate the following blocks into a single monolithic IC:
PLL (Phase-Lock-Loop)-based synthesizer
Fanout buffer
Clock generator (divider)
Logic translation (LVPECL, LVDS)

The SY89534L and SY89535L includes a flexible input design that accepts any reference input; single-ended LVTTL/CMOS, SSTL and differential LVPECL, LVDS, HSTL, and CML.This level of integration minimizes the additive jitter and part-to-part skew associated with the discrete alternative, resulting in superior system-level timing as well as reduced board space and power. For applications that must interface to a crystal oscillator, see the SY89532/33.

Additional Features
    • Integrated synthesizer plus fanout buffers, clock dividers, and translator in a single 64-pin package
    • Accepts any reference input between 14MHz to 160MHz (single-ended or differential)
    • 33MHz to 500MHz output frequency range
    • LVPECL outputs (SY89534L)
    • LVPECL and LVDS outputs (SY89535L)
    • 3.3V ±10% power supply
    • Low jitter: <50ps cycle-to-cycle
    • Low pin-to-pin skew: <50ps
    • TTL/CMOS compatible control logic
    • 3 independently programmable output frequency banks:
      • 9 differential output pairs @BankB (LVPECL/LVDS)
      • 2 differential output pairs @BankA (LVPECL)
      • 2 differential output pairs @BankC (LVPECL)
    • Available in 64-pin EPAD-TQFP
    \
Parametrics
Name
Value
Product Type
Clock Synthesizers
Input Frequency (MHz) Crystal
-
PDB
False
OE
False
FSEL
False
CSEL
False
CLK
False
Ultra Low Power
False
Output Frequency Min. (MHz)
80/480

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Data Sheets

11/11/2015
106KB

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