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SY89532L

Status: Not Recommended for new designs

Features:

  • Integrated synthesizer plus fanout buffers, clock drivers, and translator in a single 64-pin package
  • 3.3V ±10% power supply
  • Low jitter: <50ps cycle-to-cycle
  • Low pin-to-pin skew: <50ps
  • 33MHz to 500MHz output frequency range
  • Direct interface to crystal: 14MHz to 18MHz
  • LVPECL output (SY89532L), LVPECL/LVDS outputs (SY89533L)
  • TTL/CMOS compatible control logic
  • 9 differential output pairs @BankB (LVPECL/LVDS)
  • 2 differential output pairs @BankA (LVPECL)
  • 2 differential output pairs @BankC (LVPECL)
  • ExtVCO input allows synthesizer and crystal interface to be bypassed
  • Available in 64-pin EPAD-TQFP
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Device Overview

Summary

The SY89532 and SY89533L programmable clock synthesizer/drivers are a 3.3V, high-frequency, precision PLL-based clock driver family optimized for multi-frequency, multi-processor server and synchronous computing applications that require the highest precision. These devices integrate the following blocks into a single monolithic IC:
• PLL (Phase-Lock-Loop)-based synthesizer
• Fanout buffers
• Clock generator (dividers)
• Logic translation (LVPECL, LVDS)

This level of integration minimizes the additive jitter and part-to-part skew associated with the discrete alternative, resulting in superior system-level timing as well as reduced board space and power. For applications that must interface to a reference clock, see the SY89534/5.

Additional Features
    • Integrated synthesizer plus fanout buffers, clock drivers, and translator in a single 64-pin package
    • 3.3V ±10% power supply
    • Low jitter: <50ps cycle-to-cycle
    • Low pin-to-pin skew: <50ps
    • 33MHz to 500MHz output frequency range
    • Direct interface to crystal: 14MHz to 18MHz
    • LVPECL output (SY89532L), LVPECL/LVDS outputs (SY89533L)
    • TTL/CMOS compatible control logic
    • 3 independently programmable output frequency banks:
      • 9 differential output pairs @BankB (LVPECL/LVDS)
      • 2 differential output pairs @BankA (LVPECL)
      • 2 differential output pairs @BankC (LVPECL)
    • ExtVCO input allows synthesizer and crystal interface to be bypassed
    • Available in 64-pin EPAD-TQFP
Parametrics
Name
Value
Product Type
Clock Synthesizers
Input Frequency (MHz) Crystal
-
PDB
False
OE
False
FSEL
False
CSEL
False
CLK
False
Ultra Low Power
False
Output Frequency Min. (MHz)
125

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Data Sheets

11/11/2015
187KB

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