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SY89420V

Status: Not Recommended for new designs

Features:

  • 3.3V and 5V power supply options
  • 1.12GHz maximum VCO frequency
  • 30MHz to 560MHz reference input operating frequency
  • Frequency doubler mode
  • Low jitter design
  • PECL differential outputs
  • PECL and TTL reference voltages available
  • External loop filter optimizes performance/cost
  • Available in 28-pin PLCC package
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Device Overview

Summary

The SY89420V device consists of two identical, low jitter, digital Phase Locked Loops based on Micrel-Synergy's differential PLL technology. Each of the PLLs (PLLA and PLLB) is capable of operating in the 30MHz to 560MHz input reference frequency range independently of the other and is configurable separately. The PLLs can be configured to be matched in all regards, or can be configured so that PLLB is used as a frequency doubler, while PLLA is used to regenerate the undoubled frequency.

Two reference inputs (RINX and RINX), two feedback inputs (FINX and FINX), two filter pins (F1X and F2X) and two differential outputs (FOUTX and FOUTX) are provided for each of the two PLLs. The reference and feedback inputs can be used as either differential or single-ended inputs. In single-ended mode RINX and FINX can be connected to either VBB for normal 100K PECL levels or VTH for normal TTL levels.

Feedback for the loops is realized by connecting FOUTX, FOUTX to FINX, FINX by means of external circuitry. This allows the user the flexibility of inserting additional circuitry off-chip in the feedback paths, such as a divider. Pulldown resistors are required for the FOUTX and FOUTX pins.Use of a phase-frequency detector results in excellent PLL locking and tracking characteristics. Error correction voltages are generated by the detector if either phase or frequency deviations occur. The VCO has a frequency range covering more than a 2:1 ratio from 480MHz to 1120MHz.Select pins S1X and S2X are used to program the N dividers for optimum VCO operation, in other words with the VCO in the center of its range. Additional select pins, S3B and S4B, are provided for PLLB. When both S3B and S4B are low, PLLB is identical to PLLA. When S3B is high, NB can be set to 1, 10, 18, or 20. When S4B is high, the frequency doubler option is enabled (P = 2). All Select pins are TTL compatible.

Additional Features
    • 3.3V and 5V power supply options
    • 1.12GHz maximum VCO frequency
    • 30MHz to 560MHz reference input operating frequency
    • Frequency doubler mode
    • Low jitter design
    • PECL differential outputs
    • PECL and TTL reference voltages available
    • External loop filter optimizes performance/cost
    • Available in 28-pin PLCC package
Parametrics
Name
Value
Product Type
Clock Synthesizers
Input Frequency (MHz) Crystal
25
PDB
False
OE
True
FSEL
True
CSEL
False
CLK
False
Ultra Low Power
False
Output Frequency Min. (MHz)
100/200

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Data Sheets

11/11/2015
77KB

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