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SY89230U

Status: In Production

Features:

  • Accepts a high-speed input and provides a precision ÷3 and ÷5 sub-rate, LVPECL output
  • DC-to >3.2GHz throughput
  • <850ps Propagation Delay (In-to-Q)
  • <200ps Rise/Fall times
  • <1psRMS random jitter
  • <1psRMS cycle-to-cycle jitter
  • <10psPP total jitter (clock)
  • <0.7psRMS MUX crosstalk induced jitter
  • Unique patented internal termination and VT pin accepts DC- and AC-coupled inputs (CML, PECL, LVDS)
  • Wide input voltage range VCC to GND
  • 800mV LVPECL output
  • 45% to 55% Duty Cycle (÷ 3)
  • 47% to 53% Duty Cycle (÷ 5)
  • 2.5V ±5% or 3.3V ±10% supply voltage
  • -40°C to +85°C industrial temperature range
  • Available in 16-pin (3mm x 3mm) QFN package
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

The SY89230U is a precision, low jitter 3.2GHz ÷3, ÷5 clock divider with a LVPECL output. The differential input includes Micrel's unique, 3-pin internal termination architecture that allows the input to interface to any differential signal (AC- or DC-coupled) as small as 100mV (200mVPP) without any level shifting or termination resistor networks in the signal path. The outputs are 800mV, 100K-compatible LVPECL with fast rise/fall times guaranteed to be less than 200ps.The SY89230U operates from a 2.5V ±5% or 3.3V ±10% supply and is guaranteed over the full industrial temperature range of -40°C to +85°C. The SY89230U is part of Micrel's high-speed, Precision Edge® product line.

Additional Features
    • Accepts a high-speed input and provides a precision ÷3 and ÷5 sub-rate, LVPECL output
    • Guaranteed AC performance over temperature and supply voltage:
      • DC-to >3.2GHz throughput
      • <850ps Propagation Delay (In-to-Q)
      • <200ps Rise/Fall times
    • Ultra-low jitter design:
      • <1psRMS random jitter
      • <1psRMS cycle-to-cycle jitter
    • <10psPP total jitter (clock)
    • <0.7psRMS MUX crosstalk induced jitter
    • Unique patented internal termination and VT pin accepts DC- and AC-coupled inputs (CML, PECL, LVDS)
    • Wide input voltage range VCC to GND
    • 800mV LVPECL output
    • 45% to 55% Duty Cycle (÷ 3)
    • 47% to 53% Duty Cycle (÷ 5)
    • 2.5V ±5% or 3.3V ±10% supply voltage
    • -40°C to +85°C industrial temperature range
    • Available in 16-pin (3mm x 3mm) QFN package
Parametrics
Name
Value
Product Type
Divider
Description
÷3, ÷5;1 Output
Input
ANY
Output
LVPECL
Supply Voltage
2.5/3.3V
Max Freq (GHz)
3.2
Max Prop Delay (ps)
850
Icc (mA)
62
Max Within Device Skew (ps)
300
OE
False
RPE
False
FSI
True
Input Mux
False
Input EQ
False
Output Type
LVPECL

Documents

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Data Sheet

04/30/2018
470KB

User Guides


Development tools data is currently unavailable.

RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
SY89230UMG-TR
0.021300
0.801700
16
VQFN
3x3x1.00mm
NiPdAu
e4
SY89230UMG
0.021300
0.050000
16
VQFN
3x3x1.00mm
NiPdAu
e4
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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